Home
last modified time | relevance | path

Searched refs:isWave32 (Results 1 – 25 of 37) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILateBranchLowering.cpp169 TII->get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in expandChainCall()
221 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in run()
222 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in run()
H A DSIRegisterInfo.h44 bool isWave32; variable
381 return isWave32 ? &AMDGPU::SReg_32RegClass in getBoolRC()
386 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getWaveMaskRegClass()
H A DSIOptimizeExecMasking.cpp665 ST->isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64; in tryRecordVCmpxAndSaveexecSequence()
752 ST->isWave32() ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64; in tryRecordOrSaveexecXorSequence()
762 const unsigned OrSaveexecOpcode = ST->isWave32() in tryRecordOrSaveexecXorSequence()
790 const unsigned Andn2Opcode = ST->isWave32() ? AMDGPU::S_ANDN2_SAVEEXEC_B32 in optimizeOrSaveexecXorSequences()
H A DAMDGPUAtomicOptimizer.cpp409 if (ST.isWave32()) { in buildReduction()
475 if (!ST.isWave32()) { in buildScan()
520 if (!ST.isWave32()) { in buildShiftRight()
700 if (ST.isWave32()) { in optimizeAtomic()
H A DGCNCreateVOPD.cpp132 if (!AMDGPU::hasVOPD(*ST) || !ST->isWave32()) in run()
H A DGCNVOPDUtils.cpp232 if (!AMDGPU::hasVOPD(ST) || !ST.isWave32()) { in apply()
H A DSIFrameLowering.cpp821 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
957 ST.isWave32() ? (EnableInactiveLanes ? AMDGPU::S_XOR_SAVEEXEC_B32 in buildScratchExecCopy()
1001 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillStores()
1013 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillStores()
1104 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillRestores()
1116 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillRestores()
H A DGCNSubtarget.h1176 return UserSGPRInit16Bug && isWave32(); in hasUserSGPRInit16Bug()
1641 bool isWave32() const { in isWave32() function
H A DSIInstrInfo.cpp1214 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1228 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1271 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
1274 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1289 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
1292 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
2504 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in expandPostRAPseudo()
2511 const unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
2512 const unsigned WQMOp = ST.isWave32() ? AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64; in expandPostRAPseudo()
2513 const unsigned MovOp = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in expandPostRAPseudo()
[all …]
H A DSIWholeQuadMode.cpp885 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in lowerKillF32()
1001 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1()
1568 bool IsWave32 = ST->isWave32(); in lowerInitExec()
1714 if (ST->isWave32()) { in run()
H A DSIRegisterInfo.cpp332 ST(ST), SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) { in SIRegisterInfo()
2036 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR()
2164 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR()
2243 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR()
3157 if (!isWave32) in eliminateFrameIndex()
3892 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
3896 return isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in getExec()
H A DSIPreEmitPeephole.cpp91 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch()
H A DSIAnnotateControlFlow.cpp117 IntMask = ST.isWave32() ? Type::getInt32Ty(Context) in initialize()
H A DAMDGPUCallLowering.cpp1240 if (!ST.isWave32()) { in lowerTailCall()
1257 ST.isWave32(), CalleeCC, IsDynamicVGPRChainCall); in lowerTailCall()
1503 unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false, ST.isWave32(), in lowerCall()
H A DSIShrinkInstructions.cpp838 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64); in tryReplaceDeadSDST()
851 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in run()
H A DSIOptimizeExecMaskingPreRA.cpp374 const bool Wave32 = ST.isWave32(); in run()
H A DGCNSubtarget.cpp344 if (isWave32()) { in mirFileLoaded()
H A DVOP3PInstructions.td1296 let WaveSizePredicate = isWave32 in {
1654 let WaveSizePredicate = isWave32 in {
1701 } // End WaveSizePredicate = isWave32
1703 let WaveSizePredicate = isWave32 in {
1775 let WaveSizePredicate = isWave32, SubtargetPredicate = isGFX12Plus in {
1902 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in {
1914 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in {
2092 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX11" in {
H A DVOPDInstructions.td123 let WaveSizePredicate = isWave32;
H A DVOP2Instructions.td309 let WaveSizePredicate = isWave32 in {
383 let WaveSizePredicate = isWave32 in {
1664 let WaveSizePredicate = isWave32;
1692 let WaveSizePredicate = isWave32;
2124 let WaveSizePredicate = isWave32;
2149 let WaveSizePredicate = isWave32;
2173 let WaveSizePredicate = isWave32;
H A DVOPCInstructions.td322 let WaveSizePredicate = isWave32 in {
1244 let WaveSizePredicate = isWave32 in {
1331 let WaveSizePredicate = isWave32 in {
1641 let WaveSizePredicate = isWave32;
1653 let WaveSizePredicate = isWave32;
1722 let WaveSizePredicate = isWave32;
1736 let WaveSizePredicate = isWave32;
H A DDSInstructions.td802 let WaveSizePredicate = isWave32, mayStore = 0 in {
809 } // End WaveSizePredicate = isWave32, mayStore = 0
1311 let WaveSizePredicate = isWave32, SubtargetPredicate = isGFX1250Plus in {
1320 } // End WaveSizePredicate = isWave32, SubtargetPredicate = isGFX1250Plus
H A DAMDGPUAsmPrinter.cpp584 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
1529 if (MD->getPALMajorVersion() < 3 && STM.isWave32()) in EmitPALMetadata()
H A DSILowerI1Copies.cpp450 IsWave32 = ST->isWave32(); in PhiLoweringHelper()
H A DSILowerControlFlow.cpp775 if (ST.isWave32()) { in run()

12