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Searched refs:isWave32 (Results 1 – 25 of 37) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h36 bool isWave32;
346 return isWave32 ? &AMDGPU::SReg_32RegClass in getWaveMaskRegClass()
351 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
34 bool isWave32; global() variable
H A DSILateBranchLowering.cpp154 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
155 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
H A DSIOptimizeExecMasking.cpp644 ST->isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64; in tryRecordVCmpxAndSaveexecSequence()
731 ST->isWave32() ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64; in tryRecordOrSaveexecXorSequence()
741 const unsigned OrSaveexecOpcode = ST->isWave32() in tryRecordOrSaveexecXorSequence()
769 const unsigned Andn2Opcode = ST->isWave32() ? AMDGPU::S_ANDN2_SAVEEXEC_B32 in optimizeOrSaveexecXorSequences()
H A DGCNCreateVOPD.cpp122 if (!AMDGPU::hasVOPD(*ST) || !ST->isWave32()) in runOnMachineFunction()
H A DGCNVOPDUtils.cpp160 if (!AMDGPU::hasVOPD(ST) || !ST.isWave32()) { in apply()
H A DAMDGPUAtomicOptimizer.cpp428 if (ST->isWave32()) { in buildReduction()
493 if (!ST->isWave32()) { in buildScan()
538 if (!ST->isWave32()) { in buildShiftRight()
718 if (ST->isWave32()) { in optimizeAtomic()
H A DSIRegisterInfo.cpp323 ST(ST), SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) { in SIRegisterInfo()
1764 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR()
1887 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR()
1966 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR()
2506 if (!isWave32) in eliminateFrameIndex()
3102 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClassForSizeOnBank()
3127 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
3131 return isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in getExec()
3146 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
H A DSIFrameLowering.cpp774 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
910 ST.isWave32() ? (EnableInactiveLanes ? AMDGPU::S_XOR_SAVEEXEC_B32 in buildScratchExecCopy()
954 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillStores()
966 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillStores()
1057 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillRestores()
1069 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillRestores()
H A DSIInstrInfo.cpp1253 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1267 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1310 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
1313 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1328 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
1331 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
2276 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo()
2277 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
2292 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo()
2293 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
[all …]
H A DGCNSubtarget.h1129 return UserSGPRInit16Bug && isWave32(); in hasUserSGPRInit16Bug()
1528 bool isWave32() const { in isWave32() function
H A DSIWholeQuadMode.cpp873 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in lowerKillF32()
991 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1()
1527 bool IsWave32 = ST->isWave32(); in lowerInitExec()
1657 if (ST->isWave32()) { in runOnMachineFunction()
H A DAMDGPUCallLowering.cpp959 bool IsTailCall, bool isWave32, in getCallOpcode() argument
969 return isWave32 ? AMDGPU::SI_CS_CHAIN_TC_W32 : AMDGPU::SI_CS_CHAIN_TC_W64; in getCallOpcode()
1204 getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC); in lowerTailCall()
1446 unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false, ST.isWave32(), in lowerCall()
H A DSIPreEmitPeephole.cpp89 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch()
H A DVOPDInstructions.td82 let WaveSizePredicate = isWave32;
H A DSIAnnotateControlFlow.cpp129 IntMask = ST.isWave32() ? Type::getInt32Ty(Context) in initialize()
H A DSIShrinkInstructions.cpp786 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64); in tryReplaceDeadSDST()
800 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
H A DSIOptimizeExecMaskingPreRA.cpp353 const bool Wave32 = ST.isWave32(); in runOnMachineFunction()
H A DVOPCInstructions.td234 let WaveSizePredicate = isWave32 in {
1001 let WaveSizePredicate = isWave32 in {
1072 let WaveSizePredicate = isWave32 in {
1362 let WaveSizePredicate = isWave32;
1374 let WaveSizePredicate = isWave32;
1431 let WaveSizePredicate = isWave32;
1445 let WaveSizePredicate = isWave32;
H A DVOP2Instructions.td289 let WaveSizePredicate = isWave32 in {
358 let WaveSizePredicate = isWave32 in {
1439 let WaveSizePredicate = isWave32;
1467 let WaveSizePredicate = isWave32;
1866 let WaveSizePredicate = isWave32;
1891 let WaveSizePredicate = isWave32;
1915 let WaveSizePredicate = isWave32;
H A DAMDGPUInstCombineIntrinsic.cpp981 if (ST->isWave32()) in instCombineIntrinsic()
992 if (ST->isWave32() && II.getType()->getIntegerBitWidth() == 64) { in instCombineIntrinsic()
H A DAMDGPUAsmPrinter.cpp460 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
1320 if (MD->getPALMajorVersion() < 3 && STM.isWave32()) in EmitPALMetadata()
H A DSILowerI1Copies.cpp519 IsWave32 = ST->isWave32(); in PhiLoweringHelper()
H A DVOP3PInstructions.td959 let WaveSizePredicate = isWave32 in {
1224 let WaveSizePredicate = isWave32 in {
1296 let WaveSizePredicate = isWave32, SubtargetPredicate = isGFX12Plus in {
1422 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in {
1558 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX11" in {
H A DSILowerControlFlow.cpp774 if (ST.isWave32()) { in runOnMachineFunction()
H A DAMDGPURegisterBankInfo.cpp787 Subtarget.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in executeInWaterfallLoop()
789 Subtarget.isWave32() ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term; in executeInWaterfallLoop()
791 const unsigned XorTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
793 const unsigned AndSaveExecOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
795 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop()
938 {LLT::scalar(Subtarget.isWave32() ? 32 : 64)}) in executeInWaterfallLoop()

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