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Searched refs:isTypeDesirableForOp (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h379 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
H A DSIISelLowering.cpp2056 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const { in isTypeDesirableForOp() function in SITargetLowering
2072 return TargetLowering::isTypeDesirableForOp(Op, VT); in isTypeDesirableForOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h264 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
H A DAArch64ISelLowering.cpp30569 bool AArch64TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { in isTypeDesirableForOp() function in AArch64TargetLowering
30578 return TargetLowering::isTypeDesirableForOp(Opc, VT); in isTypeDesirableForOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1158 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
H A DX86ISelLowering.cpp60699 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { in isTypeDesirableForOp() function in X86TargetLowering
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1820 isTypeDesirableForOp(ISD::SHL, InnerVT)) { in SimplifyDemandedBits()
1889 isTypeDesirableForOp(ISD::SHL, SmallVT) && in SimplifyDemandedBits()
1913 isTypeDesirableForOp(ISD::SHL, HalfVT) && in SimplifyDemandedBits()
2027 isTypeDesirableForOp(ISD::SRL, HalfVT) && in SimplifyDemandedBits()
2651 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
4813 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { in SimplifySetCC()
4973 isTypeDesirableForOp(ISD::SETCC, newVT))) { in SimplifySetCC()
H A DDAGCombiner.cpp1567 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntBinOp()
1635 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteIntShiftOp()
1684 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteExtend()
1715 if (TLI.isTypeDesirableForOp(Opc, VT)) in PromoteLoad()
6174 LegalTypes && !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
7474 TLI.isTypeDesirableForOp(ISD::AND, SrcVT) && in visitAND()
10221 TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) { in distributeTruncateThroughAnd()
11102 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
11484 TLI.isTypeDesirableForOp(ISD::ABS, ExtVT) && in visitABS()
11677 TLI.isTypeDesirableForOp(ISD::CTPOP, HalfVT) && in visitCTPOP()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4521 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { in isTypeDesirableForOp() function
/freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/
H A DDemangleTestCases.inc12928 …ering20isTypeDesirableForOpEjNS_3EVTE", "llvm::X86TargetLowering::isTypeDesirableForOp(unsigned in…
14302 …Lowering20isTypeDesirableForOpEjNS_3EVTE", "llvm::TargetLowering::isTypeDesirableForOp(unsigned in…