Searched refs:isThumb1 (Results 1 – 4 of 4) sorted by relevance
117 bool isThumb1, isThumb2; member491 assert(isThumb1 && "Can only update base register uses for Thumb1!"); in UpdateBaseRegUses()639 bool SafeToClobberCPSR = !isThumb1 || in CreateLoadStoreMulti()643 bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback. in CreateLoadStoreMulti()648 if (isThumb1 && ContainsReg(Regs, Base)) { in CreateLoadStoreMulti()659 bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1; in CreateLoadStoreMulti()665 } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) { in CreateLoadStoreMulti()699 NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass); in CreateLoadStoreMulti()706 : (isThumb1 && Base == ARM::SP) in CreateLoadStoreMulti()708 : (isThumb1 && Offset < 8) in CreateLoadStoreMulti()[all …]
220 bool isThumb1; member in __anon34c212310111::ARMConstantIslands405 isThumb1 = AFI->isThumb1OnlyFunction(); in runOnMachineFunction()408 bool GenerateTBB = isThumb2 || (isThumb1 && SynthesizeThumb1TBB); in runOnMachineFunction()719 return isThumb1 ? Align(4) : Align(1); in getCPEAlign()721 return isThumb1 ? Align(4) : Align(2); in getCPEAlign()1385 unsigned Delta = isThumb1 ? 2 : 4; in createNewWater()1726 if (!isThumb1) in fixupUnconditionalBr()
1633 bool isThumb1 = Subtarget.isThumb1Only(); in expandMEMCPY() local1641 if (isThumb1 || !MI->getOperand(1).isDead()) { in expandMEMCPY()1644 : isThumb1 ? ARM::tLDMIA_UPD in expandMEMCPY()1651 if (isThumb1 || !MI->getOperand(0).isDead()) { in expandMEMCPY()1654 : isThumb1 ? ARM::tSTMIA_UPD in expandMEMCPY()
12376 bool isThumb1 = Subtarget->isThumb1Only(); in attachMEMCPYScratchRegs() local12393 Register TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass in attachMEMCPYScratchRegs()