117     bool isThumb1, isThumb2;  member
491   assert(isThumb1 && "Can only update base register uses for Thumb1!");  in UpdateBaseRegUses()
639   bool SafeToClobberCPSR = !isThumb1 ||  in CreateLoadStoreMulti()
643   bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.  in CreateLoadStoreMulti()
648   if (isThumb1 && ContainsReg(Regs, Base)) {  in CreateLoadStoreMulti()
659   bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1;  in CreateLoadStoreMulti()
665   } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) {  in CreateLoadStoreMulti()
699       NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass);  in CreateLoadStoreMulti()
706                            : (isThumb1 && Base == ARM::SP)  in CreateLoadStoreMulti()
708                                  : (isThumb1 && Offset < 8)  in CreateLoadStoreMulti()
710                                        : isThumb1 ? ARM::tADDi8 : ARM::ADDri;  in CreateLoadStoreMulti()
718                          : (isThumb1 && Offset < 8 && Base != ARM::SP)  in CreateLoadStoreMulti()
720                                : isThumb1 ? ARM::tSUBi8 : ARM::SUBri;  in CreateLoadStoreMulti()
732     if (isThumb1) {  in CreateLoadStoreMulti()
796   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)  in CreateLoadStoreMulti()
802     assert(isThumb1 && "expected Writeback only inThumb1");  in CreateLoadStoreMulti()
1291   if (isThumb1) return false;  in MergeBaseUpdateLSMultiple()
1472   if (isThumb1) return false;  in MergeBaseUpdateLoadStore()
2039   if (isThumb1) return false;  in MergeReturnIntoLDM()
2112   isThumb1 = AFI->isThumbFunction() && !isThumb2;  in runOnMachineFunction()
2119     if (isThumb1)  in runOnMachineFunction()