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Searched refs:isSignedIntN (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZOperands.td367 return N->getAPIntValue().isSignedIntN(8);
381 return N->getAPIntValue().isSignedIntN(16);
385 return (-N->getAPIntValue()).isSignedIntN(16);
487 return N->getAPIntValue().isSignedIntN(8);
495 return N->getAPIntValue().isSignedIntN(16);
499 return (-N->getAPIntValue()).isSignedIntN(16);
507 return N->getAPIntValue().isSignedIntN(32);
511 return (-N->getAPIntValue()).isSignedIntN(32);
623 def disp20imm32 : DispOp<i32, [{ return N->getAPIntValue().isSignedIntN(20); }]>;
624 def disp20imm64 : DispOp<i64, [{ return N->getAPIntValue().isSignedIntN(20); }]>;
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/PDB/Native/
H A DNativeSymbolEnumerator.cpp83 assert(Record.Value.isSignedIntN(BT.getLength() * 8)); in getValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp558 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) || in selectVSplatCommon()
1086 if (SplatValue.isSignedIntN(10)) { in trySelect()
1091 } else if (SplatValue.isSignedIntN(16) && in trySelect()
1121 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) { in trySelect()
1142 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 64 && in trySelect()
1170 } else if (SplatValue.isSignedIntN(64)) { in trySelect()
H A DMipsInstructionSelector.cpp161 if (Imm.isSignedIntN(16)) { in materialize32BitImm()
451 if (OffsetValue.isSignedIntN(16)) { in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp150 if (SplatValue.isSignedIntN(10)) { in INITIALIZE_PASS()
401 if (IsSigned && ImmValue.isSignedIntN(ImmBitSize)) { in selectVSplatImm()
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPSInt.h95 return isSigned() ? isSignedIntN(64) : isIntN(63); in isRepresentableByInt64()
H A DAPInt.h435 bool isSignedIntN(unsigned N) const { return getSignificantBits() <= N; } in isSignedIntN() function
/freebsd/contrib/llvm-project/lldb/source/Utility/
H A DScalar.cpp658 fits = integer.isSignedIntN(byte_size * 8); in SetValueFromCString()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DTargetInfo.h1167 return Value.isSignedIntN(32) && ImmSet.contains(Value.getZExtValue()); in isValidAsmImmediate()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp2898 if (!constToInt(L.Value, A) || !A.isSignedIntN(64)) in rewriteHexConstDefs()
2918 if (A.isSignedIntN(8)) { in rewriteHexConstDefs()
3020 if (!constToInt(LI.Value, A) || !A.isSignedIntN(8)) in rewriteHexConstUses()
H A DHexagonVectorCombine.cpp2736 if (V.isSignedIntN(8 * sizeof(int))) in calculatePointerDifference()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCLoopInstrFormPrep.cpp1328 if (ConstInt.isSignedIntN(16) && ConstInt.srem(4) != 0) in runOnLoop()
H A DPPCInstrInfo.cpp4568 if (III.SignedImm && !ActualValue.isSignedIntN(III.ImmWidth)) in isImmElgibleForForwarding()
5011 if (!ActualValue.isSignedIntN(III.ImmWidth)) in transformToImmFormFedByLI()
H A DPPCISelLowering.cpp18392 if (!ConstNode->getAPIntValue().isSignedIntN(64)) in decomposeMulByConstant()
19274 if (ConstImm.isSignedIntN(32)) { // Flag to handle 32-bit constants. in computeFlagsForAddressComputation()
19279 if (ConstImm.isSignedIntN(34)) // Flag to handle 34-bit constants. in computeFlagsForAddressComputation()
19293 if (ConstImm.isSignedIntN(16)) { in computeFlagsForAddressComputation()
19298 if (ConstImm.isSignedIntN(34)) in computeFlagsForAddressComputation()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp722 if (Imm->getAPIntValue().isSignedIntN(8)) in IsProfitableToFold()
747 (-Imm->getAPIntValue()).isSignedIntN(8)) in IsProfitableToFold()
751 (-Imm->getAPIntValue()).isSignedIntN(8) && in IsProfitableToFold()
H A DX86TargetTransformInfo.cpp6118 if ((Idx == 1) && Imm.getBitWidth() <= 64 && Imm.isSignedIntN(32)) in getIntImmCostIntrin()
6122 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && Imm.isSignedIntN(64))) in getIntImmCostIntrin()
6127 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && Imm.isSignedIntN(64))) in getIntImmCostIntrin()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp4574 !isIVIncrement(ScaleReg, &LI) && CI->getValue().isSignedIntN(64)) { in matchScaledValue()
4635 if (Offset.isSignedIntN(64)) { in matchScaledValue()
5446 if (CI->getValue().isSignedIntN(64)) { in matchAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1989 if (!(CI + AccumulatedOffset).isSignedIntN(32)) in accumulateOffset()
H A DNVPTXInstrInfo.td882 return v.isSignedIntN(32);
892 return v.isSignedIntN(16);
H A DNVPTXISelLowering.cpp4722 if (!APInt(64, AM.BaseOffs).isSignedIntN(32)) in isLegalAddressingMode()
5406 return Val.isSignedIntN(OptSize); in AreMulWideOperandsDemotable()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2144 return !Mask->getValue().isSignedIntN(12) && Mask->getValue().isPowerOf2(); in isMaskAndCmp0FoldingBeneficial()
15425 if (!ImmValMinus1.isSignedIntN(12)) in combineSubOfBoolean()
15924 if ((Imm + 1).isSignedIntN(12)) in performXORCombine()
18560 if (MaskVal.isPowerOf2() && !MaskVal.isSignedIntN(12)) in useInversedSetcc()
20524 !Const->getAPIntValue().sextOrTrunc(EltWidth).isSignedIntN(5))) in PerformDAGCombine()
20870 if (ShrunkMask.isSignedIntN(12)) in targetShrinkDemandedConstant()
20903 else if (!C->isOpaque() && MinSignedBits <= 32 && !ShrunkMask.isSignedIntN(32)) in targetShrinkDemandedConstant()
23792 if (Subtarget.hasVendorXqciac() && Imm.isSignedIntN(12)) in decomposeMulByConstant()
23801 if (Subtarget.hasStdExtZba() && !Imm.isSignedIntN(12) && in decomposeMulByConstant()
23808 if (!Imm.isSignedIntN(12) && Imm.countr_zero() < 12 && in decomposeMulByConstant()
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/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DAPInt.cpp977 if (isSignedIntN(width)) in truncSSat()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1968 if (!Mask.isSignedIntN(32)) // Avoid large immediates. in EmitTest()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstructionCombining.cpp4197 : CaseVal.isSignedIntN(NewWidth); in visitSwitchInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp5128 if (!IsXReg && !(Simm.isIntN(32) || Simm.isSignedIntN(32))) in parseOperand()

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