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Searched refs:isShiftedUInt (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td24 defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
27 defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
75 defm u1_0ImmPred : ImmOpPred<[{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>;
78 defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>;
81 defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>;
84 defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>;
87 defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>;
90 defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>;
93 defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>;
96 defm u4_0ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>;
[all …]
H A DHexagonInstrInfo.cpp2832 return isShiftedUInt<6,1>(Offset); in isValidOffset()
2837 return isShiftedUInt<6,2>(Offset); in isValidOffset()
2933 return isShiftedUInt<6,1>(Offset); in isValidOffset()
2939 return isShiftedUInt<6,2>(Offset); in isValidOffset()
2945 return isShiftedUInt<6,3>(Offset); in isValidOffset()
3950 isShiftedUInt<5,2>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3955 isShiftedUInt<4,2>(MI.getOperand(2).getImm()))) in getDuplexCandidateGroup()
3987 isShiftedUInt<3,1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4009 isShiftedUInt<5,3>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
4072 isShiftedUInt<5,2>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXwch.td30 ImmLeaf<XLenVT, [{return isShiftedUInt<4, 1>(Imm);}]> {
39 return isShiftedUInt<4, 1>(Imm);
45 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 1>(Imm);}]> {
54 return isShiftedUInt<5, 1>(Imm);
H A DRISCVInstrInfoZc.td19 ImmLeaf<XLenVT, [{return isShiftedUInt<1, 1>(Imm);}]> {
28 return isShiftedUInt<1, 1>(Imm);
85 return isShiftedUInt<2, 4>(Imm);
97 return isShiftedUInt<2, 4>(Imm);
H A DRISCVInstrInfoC.td97 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
106 return isShiftedUInt<5, 2>(Imm);
112 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
121 return isShiftedUInt<6, 2>(Imm);
127 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
136 return isShiftedUInt<5, 3>(Imm);
158 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {
167 return isShiftedUInt<6, 3>(Imm);
175 [{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {
184 return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
H A DRISCVMakeCompressible.cpp170 return isShiftedUInt<6, 2>(Offset); in compressibleSPOffset()
172 return isShiftedUInt<6, 3>(Offset); in compressibleSPOffset()
H A DRISCVInstrInfoXMips.td19 ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> {
28 return isShiftedUInt<4, 3>(Imm);
H A DRISCVInstrInfo.cpp2818 Ok = isShiftedUInt<1, 1>(Imm); in verifyInstruction()
2821 Ok = isShiftedUInt<4, 1>(Imm); in verifyInstruction()
2833 Ok = isShiftedUInt<5, 1>(Imm); in verifyInstruction()
2836 Ok = isShiftedUInt<5, 2>(Imm); in verifyInstruction()
2839 Ok = isShiftedUInt<4, 3>(Imm); in verifyInstruction()
2842 Ok = isShiftedUInt<6, 2>(Imm); in verifyInstruction()
2845 Ok = isShiftedUInt<5, 3>(Imm); in verifyInstruction()
2851 Ok = isShiftedUInt<6, 3>(Imm); in verifyInstruction()
2857 Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0); in verifyInstruction()
H A DRISCVInstrInfoXTHead.td687 return isShiftedUInt<2, 3>(Imm);
696 return isShiftedUInt<2, 4>(Imm);
H A DRISCVInstrInfoXqci.td101 ImmLeaf<XLenVT, [{return isShiftedUInt<12, 2>(Imm);}]> {
H A DRISCVISelLowering.cpp17594 if ((Offset1 + 4 == Offset2) && isShiftedUInt<2, 3>(Offset1)) in performMemPairCombine()
17598 if ((Offset1 + 8 == Offset2) && isShiftedUInt<2, 4>(Offset1)) in performMemPairCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td114 ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(Imm);"> {
124 ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(-Imm);"> {
150 ImmLeaf<i32, "return isShiftedUInt<16, 16>(Imm);", uimm32_hi16> {
333 return isShiftedUInt<5, 0>(Imm);
345 return isShiftedUInt<5, 1>(Imm);
353 return isShiftedUInt<5, 2>(Imm);
364 return isShiftedUInt<7, 2>(Imm);
373 return isShiftedUInt<8, 0>(Imm);
381 return isShiftedUInt<8, 2>(Imm);
393 return isShiftedUInt<1
[all...]
H A DCSKYInstrInfo.cpp241 } else if (isShiftedUInt<16, 16>(Val)) { in movImm()
H A DCSKYFrameLowering.cpp555 } else if (!STI.hasE2() && isShiftedUInt<7, 2>(std::abs(Val))) { in adjustReg()
H A DCSKYInstrInfoF1.td68 "return isShiftedUInt<"#width#", "#shift#">(N->getValueAPF().bitcastToAPInt().getZExtValue());">;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h205 return isShiftedUInt<N, S>(minConstant(MCI, Index)); in inRange()
H A DHexagonMCDuplexInfo.cpp561 if (!isShiftedUInt<6, 0>(Value)) in subInstWouldBeExtended()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp217 return isShiftedUInt<23, 2>(static_cast<int32_t>(Value)); in isBrImm()
231 return Value != 0 && isShiftedUInt<16, 16>(Value); in isHiImm16()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp247 return IsConstantImm && isShiftedUInt<num, shift>(Imm); in isUImm()
395 return isShiftedUInt<6, 0>(Imm) && uimm4 >= 0 && uimm4 <= 14; in isExtImm6()
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h211 constexpr bool isShiftedUInt(uint64_t x) { in isShiftedUInt() function
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp698 return IsConstantImm && isShiftedUInt<N, S>(Imm); in isUImmShifted()
850 [](int64_t Imm) { return isShiftedUInt<8, 2>(Imm) && (Imm != 0); }); in isUImm10Lsb00NonZero()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td131 return isShiftedUInt<22, 10>(N->getZExtValue());
137 return N->hasOneUse() && isShiftedUInt<22, 10>(~(unsigned)N->getZExtValue());
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp19482 return isShiftedUInt<7,2>(V); in isLegalT2AddressImmediate()
19485 return isShiftedUInt<7,1>(V); in isLegalT2AddressImmediate()
19495 return isShiftedUInt<8, 1>(V); in isLegalT2AddressImmediate()
19498 return isShiftedUInt<8, 2>(V); in isLegalT2AddressImmediate()
19543 return isShiftedUInt<8, 2>(V); in isLegalAddressImmediate()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1355 isShiftedUInt<Bits, ShiftLeftAmount>(getConstantImm()); in isScaledUImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12706 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal)) in LowerAsmOperandForConstraint()
12711 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) { in LowerAsmOperandForConstraint()

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