Home
last modified time | relevance | path

Searched refs:isSExt (Results 1 – 25 of 28) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineFrameInfo.h180 bool isSExt = false; member
551 return Objects[ObjectIdx+NumFixedObjects].isSExt; in isObjectSExt()
557 Objects[ObjectIdx+NumFixedObjects].isSExt = IsSExt; in setObjectSExt()
H A DTargetCallingConv.h76 bool isSExt() const { return IsSExt; } in isSExt() function
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp65 return LiveIn.second.isSExt(); in isLiveInSExt()
H A DPPCISelDAGToDAG.cpp832 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in tryTLSXFormLoad() local
843 Opcode = isSExt ? PPC::LHAXTLS_32 : PPC::LHZXTLS_32; in tryTLSXFormLoad()
845 Opcode = isSExt ? PPC::LHAXTLS : PPC::LHZXTLS; in tryTLSXFormLoad()
850 Opcode = isSExt ? PPC::LWAXTLS_32 : PPC::LWZXTLS_32; in tryTLSXFormLoad()
852 Opcode = isSExt ? PPC::LWAXTLS : PPC::LWZXTLS; in tryTLSXFormLoad()
5570 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
5573 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5579 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
5585 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5590 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
[all …]
H A DPPCISelLowering.cpp4483 if (Flags.isSExt()) in extendArgForPPC64()
6138 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in LowerCall_32SVR4()
6454 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
6932 LocInfo = ArgFlags.isSExt() ? CCValAssign::LocInfo::SExt in CC_AIX()
7119 if (Flags.isSExt()) in truncateScalarIntegerArg()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp870 bool isSExt = false; in select() local
874 isSExt = true; in select()
888 if (isSExt) { in select()
H A DARMFastISel.cpp2138 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in SelectRet()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp587 MachineIRBuilder &B, bool isSExt, Register DstReg, in applyPushAddSubExt() argument
591 unsigned Opc = isSExt ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in applyPushAddSubExt()
H A DAArch64CallLowering.cpp396 if (MRI.getType(CurVReg).getSizeInBits() == 1 && !Flags.isSExt() && in lowerReturn()
686 if (!Flags.isZExt() && !Flags.isSExt()) { in lowerFormalArguments()
1286 if (OrigArg.Ty->isIntegerTy(1) && !Flags.isSExt() && !Flags.isZExt()) { in lowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td16 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
H A DAMDGPUCallLowering.cpp331 if (RetInfo.Flags[0].isSExt()) { in lowerReturnVal()
H A DSIISelLowering.cpp2024 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) && in convertArgType()
2973 Ins[i].Flags.isSExt(), &Ins[i]); in LowerFormalArguments()
3023 Ins[i].Flags.isSExt(), &Ins[i]); in LowerFormalArguments()
3029 Alignment, Ins[i].Flags.isSExt(), &Ins[i]); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp402 if (Flags.isSExt()) { in buildCopyFromRegs()
667 if (Flags.isSExt()) in extendOpFromFlags()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td12 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp150 if (ArgFlags.isSExt()) in CC_Xtensa_Custom()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1252 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1256 if (Outs[0].Flags.isSExt()) in X86SelectRet()
3295 if (Flags.isSExt()) in fastLowerCall()
H A DX86ISelLoweringCall.cpp2717 Flags.isSExt() != MFI.isObjectSExt(FI)) { in MatchingStackOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1791 Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall()
1804 StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND in LowerCall()
3321 unsigned Extend = Ins[InsIdx].Flags.isSExt() ? ISD::SIGN_EXTEND in LowerFormalArguments()
3418 Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerReturn()
3441 RetVal = DAG.getNode(Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp380 if (ArgFlags.isSExt()) in CC_Lanai32_VarArg()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp507 if (ArgFlags.isSExt()) in AnalyzeArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1750 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
H A DMipsISelLowering.cpp2911 if (ArgFlags.isSExt()) in CC_MipsO32()
2923 if (ArgFlags.isSExt()) in CC_MipsO32()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp937 bool isSExt; in getCopyFromRegs() local
941 isSExt = false; in getCopyFromRegs()
945 isSExt = true; in getCopyFromRegs()
951 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp373 Flags.isSExt() != MFI.isObjectSExt(FI)) { in MatchingStackOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3920 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()

12