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Searched refs:isSExt (Results 1 – 25 of 30) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineFrameInfo.h182 bool isSExt = false; member
553 return Objects[ObjectIdx+NumFixedObjects].isSExt; in isObjectSExt()
559 Objects[ObjectIdx+NumFixedObjects].isSExt = IsSExt; in setObjectSExt()
H A DTargetCallingConv.h77 bool isSExt() const { return IsSExt; } in isSExt() function
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp65 return LiveIn.second.isSExt(); in isLiveInSExt()
H A DPPCISelDAGToDAG.cpp832 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in tryTLSXFormLoad() local
843 Opcode = isSExt ? PPC::LHAXTLS_32 : PPC::LHZXTLS_32; in tryTLSXFormLoad()
845 Opcode = isSExt ? PPC::LHAXTLS : PPC::LHZXTLS; in tryTLSXFormLoad()
850 Opcode = isSExt ? PPC::LWAXTLS_32 : PPC::LWZXTLS_32; in tryTLSXFormLoad()
852 Opcode = isSExt ? PPC::LWAXTLS : PPC::LWZXTLS; in tryTLSXFormLoad()
5583 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; in Select() local
5586 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5592 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; in Select()
5598 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
5603 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; in Select()
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H A DPPCISelLowering.cpp4498 if (Flags.isSExt()) in extendArgForPPC64()
6152 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in LowerCall_32SVR4()
6467 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4()
6944 LocInfo = ArgFlags.isSExt() ? CCValAssign::LocInfo::SExt in CC_AIX()
7131 if (Flags.isSExt()) in truncateScalarIntegerArg()
7243 bool ArgSignExt = Ins[VA.getValNo()].Flags.isSExt(); in LowerFormalArguments_AIX()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp870 bool isSExt = false; in select() local
874 isSExt = true; in select()
888 if (isSExt) { in select()
H A DARMFastISel.cpp2200 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in SelectRet()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td16 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
H A DAMDGPUCallLowering.cpp323 if (RetInfo.Flags[0].isSExt()) { in lowerReturnVal()
H A DSIISelLowering.cpp2132 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) && VT.bitsLT(MemVT)) { in convertArgType()
3079 Ins[i].Flags.isSExt(), &Ins[i]); in LowerFormalArguments()
3129 Ins[i].Flags.isSExt(), &Ins[i]); in LowerFormalArguments()
3148 Alignment, Ins[i].Flags.isSExt(), &Ins[i]); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp586 MachineIRBuilder &B, bool isSExt, Register DstReg, in applyPushAddSubExt() argument
590 unsigned Opc = isSExt ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; in applyPushAddSubExt()
H A DAArch64CallLowering.cpp446 !Flags.isSExt() && !Flags.isZExt()) { in lowerReturn()
735 if (!Flags.isZExt() && !Flags.isSExt()) { in lowerFormalArguments()
1335 if (OrigArg.Ty->isIntegerTy(1) && !Flags.isSExt() && !Flags.isZExt()) { in lowerCall()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp401 if (Flags.isSExt()) { in buildCopyFromRegs()
666 if (Flags.isSExt()) in extendOpFromFlags()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td12 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1251 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1255 if (Outs[0].Flags.isSExt()) in X86SelectRet()
3336 if (Flags.isSExt()) in fastLowerCall()
H A DX86ISelLoweringCall.cpp2772 Flags.isSExt() != MFI.isObjectSExt(FI)) { in MatchingStackOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp386 if (ArgFlags.isSExt()) in AnalyzeArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp370 if (ArgFlags.isSExt()) in CC_Lanai32_VarArg()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp363 if (ArgFlags.isSExt()) in CC_Xtensa_Custom()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1762 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
H A DMipsISelLowering.cpp3063 if (ArgFlags.isSExt()) in CC_MipsO32()
3075 if (ArgFlags.isSExt()) in CC_MipsO32()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp933 bool isSExt; in getCopyFromRegs() local
937 isSExt = false; in getCopyFromRegs()
941 isSExt = true; in getCopyFromRegs()
947 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp375 Flags.isSExt() != MFI.isObjectSExt(FI)) { in MatchingStackOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3918 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1446 if (Flags.isSExt()) in getExtOpcode()

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