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Searched refs:isSEXTLoad (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9470 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) in isSignExtended()
9563 assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) && in SkipExtensionForVMULL()
9568 unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in SkipExtensionForVMULL()
19786 bool isSEXTLoad, SDValue &Base, in getARMIndexedAddressParts() argument
19792 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { in getARMIndexedAddressParts()
19845 bool isSEXTLoad, SDValue &Base, in getT2IndexedAddressParts() argument
19870 bool isSEXTLoad, bool IsMasked, bool isLE, in getMVEIndexedAddressParts() argument
19936 bool isSEXTLoad = false; in getPreIndexedAddressParts() local
19942 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
19951 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h3195 inline bool isSEXTLoad(const SDNode *N) {
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp3793 else if (ISD::isSEXTLoad(Op.getNode())) in computeKnownBits()
H A DDAGCombiner.cpp7284 (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) { in visitAND()
13257 bool isAExtLoad = (ExtLoadType == ISD::SEXTLOAD) ? ISD::isSEXTLoad(N0Node) in tryToFoldExtOfExtload()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp9439 if (ISD::isSEXTLoad(InputNode)) in isValidSplatLoad()