Lines Matching refs:isSEXTLoad

9470   if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))  in isSignExtended()
9563 assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) && in SkipExtensionForVMULL()
9568 unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in SkipExtensionForVMULL()
19786 bool isSEXTLoad, SDValue &Base, in getARMIndexedAddressParts() argument
19792 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { in getARMIndexedAddressParts()
19845 bool isSEXTLoad, SDValue &Base, in getT2IndexedAddressParts() argument
19870 bool isSEXTLoad, bool IsMasked, bool isLE, in getMVEIndexedAddressParts() argument
19936 bool isSEXTLoad = false; in getPreIndexedAddressParts() local
19942 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
19951 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPreIndexedAddressParts()
19966 Ptr.getNode(), VT, Alignment, isSEXTLoad, IsMasked, in getPreIndexedAddressParts()
19970 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, in getPreIndexedAddressParts()
19973 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, in getPreIndexedAddressParts()
19994 bool isSEXTLoad = false, isNonExt; in getPostIndexedAddressParts() local
20000 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
20011 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
20045 getMVEIndexedAddressParts(Op, VT, Alignment, isSEXTLoad, IsMasked, in getPostIndexedAddressParts()
20050 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, in getPostIndexedAddressParts()
20053 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, in getPostIndexedAddressParts()