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Searched refs:isReturn (Results 1 – 25 of 104) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h75 virtual bool isReturn(const MCInst &Inst) const { in isReturn() function
76 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
85 if (isBranch(Inst) || isCall(Inst) || isReturn(Inst) || in mayAffectControlFlow()
H A DMCInstrDesc.h276 bool isReturn() const { return Flags & (1ULL << MCID::Return); } in isReturn() function
458 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp199 assert((!MI->isCall() && !MI->isReturn()) && in delayHasHazard()
228 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() in insertDefsUses()
248 if (MI->isCall() || MI->isReturn()) in insertDefsUses()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp149 assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && in runOnMachineFunction()
201 if (MI.isReturn() && !MI.isCall()) { in cyclesUntilReturn()
H A DX86InstrControl.td21 let isTerminator = 1, isReturn = 1, isBarrier = 1,
276 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
298 let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
349 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
396 let isTerminator = 1, isReturn = 1, isBarrier = 1 in {
422 let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
H A DX86AvoidTrailingCall.cpp79 return MI.isCall() && !MI.isReturn(); in isCallInstruction()
H A DX86VZeroUpper.cpp208 bool IsReturn = MI.isReturn(); in processBasicBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMCTargetDesc.cpp133 bool isReturn(const MCInst &Inst) const override { in isReturn() function in __anond44693ea0111::LoongArchMCInstrAnalysis
134 if (MCInstrAnalysis::isReturn(Inst)) in isReturn()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DXRayInstrumentation.cpp97 if (T.isReturn() && in replaceRetWithPatchableRet()
130 if (T.isReturn() && in prependRetWithPatchableExit()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrCall.td69 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in
76 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in
H A DWebAssemblyInstrControl.td96 let isReturn = 1 in {
106 } // isReturn = 1
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp22 if (isBranch() || isCall() || isReturn() || isIndirectBranch()) in mayAffectControlFlow()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMOptimizeBarriersPass.cpp47 MI->isReturn()); in CanMovePastDMB()
H A DARMSLSHardening.cpp278 assert(isIndirectCall(IndirectCall) && !IndirectCall.isReturn()); in ConvertIndirectCallToIndirectJump()
373 if (isIndirectCall(MI) && !MI.isReturn()) { in hardenIndirectCalls()
H A DThumb2ITBlockPass.cpp235 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { in InsertITInstructions()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp259 bool isReturn(const MCInst &Inst) const override { in isReturn() function in __anon4993c57e0111::RISCVMCInstrAnalysis
260 if (MCInstrAnalysis::isReturn(Inst)) in isReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrControl.td307 let isReturn = 1 in
313 let isReturn = 1 in
324 let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
337 } // isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp211 } else if (I->isReturn()) { in analyzeBranch()
222 isJumpOpcode(I->getOpcode()) || I->isReturn())) { in analyzeBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonShuffler.cpp502 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in GetPacketSummary()
561 if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn()) in GetPacketSummary()
563 if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) in GetPacketSummary()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td255 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
260 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
266 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
319 let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1,
374 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DInstrDocsEmitter.cpp110 FLAG(isReturn) in EmitInstrDocs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp293 if (!MI.isReturn() && !MI.isCall()) in instrumentControlFlow()
316 if (MI.isReturn()) in instrumentControlFlow()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZc.td229 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
236 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1,
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenInstruction.h242 bool isReturn : 1; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSOPInstructions.td64 let isReturn = ps.isReturn;
321 let isReturn = 1 in {
995 let isReturn = ps.isReturn;
1456 let isReturn = ps.isReturn;
1498 let isReturn = 1;
1507 let isReturn = 1;
1511 let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
1514 } // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1
1518 let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
1521 } // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1

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