Searched refs:isFP64bit (Results 1 – 15 of 15) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSubtarget.cpp | 110 if (hasMSA() && !isFP64bit()) in MipsSubtarget() 115 if (isFP64bit() && !hasMips64() && hasMips32() && !hasMips32r2()) in MipsSubtarget() 149 assert(isFP64bit()); in MipsSubtarget()
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H A D | MipsRegisterInfo.cpp | 114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs() 136 if (Subtarget.isFP64bit()) in getCallPreservedMask() 181 if (Subtarget.isFP64bit()) { in getReservedRegs()
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H A D | MipsCallingConv.td | 109 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>, 110 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>> 117 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>, 118 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>> 225 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", 228 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()", 235 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
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H A D | MipsInstructionSelector.cpp | 137 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in getRegClassForTypeOnBank() 231 if (STI.isFP64bit()) in selectLoadStoreOpCode() 550 STI.isFP64bit() ? Mips::ExtractElementF64_64 : Mips::ExtractElementF64; in select() 613 STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, in select() 626 : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32; in select() 644 Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32; in select() 875 : STI.isFP64bit() ? Mips::FCMP_D64 : Mips::FCMP_D32; in select()
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H A D | MipsSubtarget.h | 289 bool isFP64bit() const { return IsFP64bit; } in isFP64bit() function
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H A D | MipsSEFrameLowering.cpp | 315 !Subtarget.isFP64bit()); in expandBuildPairF64() 381 !Subtarget.isFP64bit()); in expandExtractElementF64()
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H A D | MipsSEInstrInfo.cpp | 770 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); in expandExtractElementF64() 824 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); in expandBuildPairF64()
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H A D | MipsFastISel.cpp | 257 UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat(); in MipsFastISel() 1156 if (Subtarget->isFP64bit()) in processCallArgs() 1166 if (Subtarget->isFP64bit()) in processCallArgs()
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H A D | MipsSEISelDAGToDAG.cpp | 787 } else if (Subtarget->isFP64bit()) { in trySelect() 973 Opc = (Subtarget->isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32); in trySelect()
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H A D | MipsSEISelLowering.cpp | 168 if (Subtarget.isFP64bit()) in MipsSETargetLowering() 252 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6"); in MipsSETargetLowering() 3209 assert(Subtarget.isFP64bit()); in emitCOPY_FD() 3274 assert(Subtarget.isFP64bit()); in emitINSERT_FD() 3469 assert(Subtarget.isFP64bit()); in emitFILL_FD()
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H A D | MipsAsmPrinter.cpp | 787 if ((ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit())) || in emitStartOfAsmFile()
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H A D | MipsInstrFPU.td | 65 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 67 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
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H A D | MipsISelLowering.cpp | 4113 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; in parseRegForInlineAsmConstraint() 4173 if (Subtarget.isFP64bit()) in getRegForInlineAsmConstraint()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsABIFlagsSection.h | 137 CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setCPR1SizeFromPredicates() 185 else if (P.isFP64bit()) in setFpAbiFromPredicates()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 580 bool isFP64bit() const { in isFP64bit() function in __anona2e40b320211::MipsAsmParser
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