| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | GenericUniformityInfo.h | 61 bool isDivergent(ConstValueRefT V) const;
64 bool isUniform(ConstValueRefT V) const { return !isDivergent(V); }
70 bool isUniform(const InstructionT *I) const { return !isDivergent(I); };
71 bool isDivergent(const InstructionT *I) const; in isUniform()
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| H A D | GenericUniformityImpl.h | 381 bool isDivergent(const InstructionT &I) const { in isDivergent() function
389 bool isDivergent(ConstValueRefT V) const { return DivergentValues.count(V); } in isDivergent() function
1109 assert(isDivergent(DivVal) && "Worklist invariant violated!"); in compute()
1127 assert(isDivergent(*I) && "Worklist invariant violated!"); in compute()
1190 if (isDivergent(value)) in print()
1226 bool GenericUniformityInfo<ContextT>::isDivergent(ConstValueRefT V) const { in isDivergent() function
1227 return DA->isDivergent(V); in isDivergent()
1231 bool GenericUniformityInfo<ContextT>::isDivergent(const InstructionT *I) const { in isDivergent() function
1232 return DA->isDivergent(*I); in isDivergent()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineUniformityAnalysis.cpp | 24 if (isDivergent(op.getReg())) in hasDivergentDefs()
70 assert(isDivergent(Reg)); in pushUsers()
85 if (isDivergent(Reg)) in pushUsers()
120 if (isDivergent(Reg)) in propagateTemporalDivergence()
137 if (isDivergent(Reg)) in isDivergentUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | UniformityAnalysis.cpp | 24 return isDivergent((const Value *)&I); in hasDivergentDefs()
83 if (isDivergent(I)) in propagateTemporalDivergence()
97 if (isDivergent(V)) in isDivergentUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURewriteUndefForPHI.cpp | 107 if (UA.isDivergent(&PHI)) in INITIALIZE_PASS_DEPENDENCY()
149 !UA.isDivergent(DominateBB->getTerminator())) in INITIALIZE_PASS_DEPENDENCY()
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| H A D | AMDGPUISelDAGToDAG.cpp | 875 unsigned Opc = OpcMap[0][N->isDivergent()][IsAdd]; in SelectADD_SUB_I64()
876 unsigned CarryOpc = OpcMap[1][N->isDivergent()][IsAdd]; in SelectADD_SUB_I64()
918 if (N->isDivergent()) { in SelectAddcSubb()
937 bool IsVALU = N->isDivergent(); in SelectUADDO_USUBO()
1373 if (N2->isDivergent()) { in SelectMUBUF()
1374 if (N3->isDivergent()) { in SelectMUBUF()
1390 } else if (N0->isDivergent()) { in SelectMUBUF()
1781 } else if (!LHS->isDivergent()) { in SelectGlobalSAddr()
1820 if (!LHS->isDivergent()) { in SelectGlobalSAddr()
1828 if (!SAddr && !RHS->isDivergent()) { in SelectGlobalSAddr()
[all …]
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| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 109 if (MRI->getType(Dst) == S1 && MUI->isDivergent(Dst)) in getCandidatesForLowering()
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| H A D | SIISelLowering.cpp | 3536 if (Callee->isDivergent()) in isEligibleForTailCallOptimization()
4193 if (Op->isDivergent()) in lowerPREFETCH()
6372 if (!Offset->isDivergent()) { in ReplaceNodeResults()
6656 … Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent())); in LowerRETURNADDR()
6780 if (Op->isDivergent()) in lowerMUL()
6842 if (Op->isDivergent()) { in lowerXMUL_LOHI()
8280 if (!Offset->isDivergent()) { in lowerSBuffer()
9819 if (Addr->isDivergent() && Addr.getOpcode() == ISD::ADD) { in LowerINTRINSIC_VOID()
9823 if (LHS->isDivergent()) in LowerINTRINSIC_VOID()
9826 if (!LHS->isDivergent() && RHS.getOpcode() == ISD::ZERO_EXTEND && in LowerINTRINSIC_VOID()
[all …]
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| H A D | SOPInstructions.td | 160 [{ return !N->isDivergent(); }]> {
172 [{ return !N->isDivergent(); }]> {
184 [{ return !N->isDivergent(); }]> {
196 [{ return N->isDivergent(); }]> {
1901 [{ return !N->isDivergent(); }]
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| H A D | SIISelLowering.h | 554 bool isDivergent) const override;
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| H A D | VOP3Instructions.td | 460 if (!N->isDivergent())
465 // Note: Use !isDivergent as a conservative proxy for whether the value
469 if (!Operands[i]->isDivergent() &&
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| H A D | VOPInstructions.td | 1064 [{ return N->isDivergent(); }]
1084 [{ return N->isDivergent(); }]> {
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| H A D | AMDGPUISelLowering.cpp | 3156 bool Is64BitScalar = !Src->isDivergent() && Src.getValueType() == MVT::i64; in LowerCTLZ_CTTZ()
4268 if (!N->isDivergent()) in performMulCombine()
4406 if (Subtarget->hasSMulHi() && !N->isDivergent()) in performMulhsCombine()
4439 if (Subtarget->hasSMulHi() && !N->isDivergent()) in performMulhuCombine()
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| H A D | SMInstructions.td | 855 [{ return !N->getOperand(1)->isDivergent();}]> {
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| H A D | SIInstructions.td | 18 [{ return !N->isDivergent(); }]>;
23 [{ return N->isDivergent(); }]>;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 371 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() argument
372 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent)); in CreateReg()
382 Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) { in CreateRegs() argument
392 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
400 return CreateRegs(V->getType(), UA && UA->isDivergent(V) && in CreateRegs()
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| H A D | InstrEmitter.cpp | 107 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
214 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC)))); in CreateVirtualRegisters()
276 Op.getSimpleValueType(), Op.getNode()->isDivergent()); in getVR()
420 Op.getNode()->isDivergent() || in AddOperand()
477 MVT VT, bool isDivergent, const DebugLoc &DL) { in ConstrainForSubReg() argument
492 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
527 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
562 Node->isDivergent(), Node->getDebugLoc()); in EmitSubregNode()
598 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
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| H A D | InstrEmitter.h | 86 bool isDivergent, const DebugLoc &DL);
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| H A D | SelectionDAGDumper.cpp | 918 OS << " # D:" << isDivergent(); in print_details()
1156 if (isDivergent() && !VerboseDAGDumping) in print()
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| H A D | SelectionDAG.cpp | 11356 if (To->isDivergent() != From->isDivergent()) in ReplaceAllUsesWith()
11414 if (To->isDivergent() != From->isDivergent()) in ReplaceAllUsesWith()
11464 To_IsDivergent |= ToOp->isDivergent(); in ReplaceAllUsesWith()
11467 if (To_IsDivergent != From->isDivergent()) in ReplaceAllUsesWith()
11528 if (To->isDivergent() != From->isDivergent()) in ReplaceAllUsesOfValueWith()
11589 if (Op.Val.getValueType() != MVT::Other && Op.getNode()->isDivergent()) in calculateDivergence()
11631 assert(calculateDivergence(N) == N->isDivergent() && in VerifyDAGDivergence()
13129 IsDivergent |= Ops[I].getNode()->isDivergent(); in createOperands()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | FunctionLoweringInfo.h | 212 Register CreateReg(MVT VT, bool isDivergent = false);
216 Register CreateRegs(Type *Ty, bool isDivergent = false);
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| H A D | TargetLowering.h | 1026 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
1027 (void)isDivergent;
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| H A D | SelectionDAGNodes.h | 738 bool isDivergent() const { return SDNodeBits.IsDivergent; }
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 580 getRegClassFor(MVT VT, bool isDivergent = false) const override;
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| H A D | ARMISelLowering.cpp | 1928 ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const { in getRegClassFor()
1929 (void)isDivergent; in getRegClassFor()
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