3536   if (Callee->isDivergent())  in isEligibleForTailCallOptimization()
4193   if (Op->isDivergent())  in lowerPREFETCH()
6372       if (!Offset->isDivergent()) {  in ReplaceNodeResults()
6656 … Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));  in LowerRETURNADDR()
6780   if (Op->isDivergent())  in lowerMUL()
6842   if (Op->isDivergent()) {  in lowerXMUL_LOHI()
8280   if (!Offset->isDivergent()) {  in lowerSBuffer()
9819     if (Addr->isDivergent() && Addr.getOpcode() == ISD::ADD) {  in LowerINTRINSIC_VOID()
9823       if (LHS->isDivergent())  in LowerINTRINSIC_VOID()
9826       if (!LHS->isDivergent() && RHS.getOpcode() == ISD::ZERO_EXTEND &&  in LowerINTRINSIC_VOID()
9835     if (!Addr->isDivergent()) {  in LowerINTRINSIC_VOID()
10176   if (Ld->getAlign() < Align(4) || Ld->isDivergent())  in widenLoad()
10322     if (!Op->isDivergent() && Alignment >= Align(4) && NumElements < 32) {  in LowerLOAD()
10337     if (Subtarget->getScalarizeGlobalBehavior() && !Op->isDivergent() &&  in LowerLOAD()
11643       N->isDivergent() && TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32_e64) != -1) {  in performAndCombine()
12323       N->isDivergent() && TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32_e64) != -1) {  in performOrCombine()
13369       EltSize, NumElem, Idx->isDivergent(), getSubtarget());  in shouldExpandVectorDynExt()
13623   if (!(Op0->isDivergent() ^ Op1->isDivergent()))  in reassociateScalarOps()
13626   if (Op0->isDivergent())  in reassociateScalarOps()
13634   if (!(Op1->isDivergent() ^ Op2->isDivergent()))  in reassociateScalarOps()
13637   if (Op1->isDivergent())  in reassociateScalarOps()
13678   if (!N->isDivergent() && Subtarget->hasSMulHi())  in tryFoldToMad64_32()
14716     if (N->getValueType(0) == MVT::i32 && N->isDivergent() &&  in PerformDAGCombine()
15075         getRegClassFor(VT, Src0.getNode()->isDivergent());  in PostISelFolding()
15972       return UA->isDivergent(V);  in isSDNodeSourceOfDivergence()
16343 SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {  in getRegClassFor()
16346   if (RC == &AMDGPU::VReg_1RegClass && !isDivergent)  in getRegClassFor()
16349   if (!TRI->isSGPRClass(RC) && !isDivergent)  in getRegClassFor()
16351   if (TRI->isSGPRClass(RC) && isDivergent)  in getRegClassFor()
16454   if (N0->isDivergent() || !N1->isDivergent())  in isReassocProfitable()