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Searched refs:isBeforeLegalizeOps (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp588 if (DCI.isBeforeLegalizeOps()) in performDivRemCombine()
697 if (DCI.isBeforeLegalizeOps()) in performSELECTCombine()
778 if (DCI.isBeforeLegalizeOps()) in performCMovFPCombine()
805 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
888 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
1125 if (DCI.isBeforeLegalizeOps()) { in performSUBCombine()
1140 if (DCI.isBeforeLegalizeOps()) { in performADDCombine()
1182 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) in performSHLCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp651 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
667 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
3109 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
4221 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
4695 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4704 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4970 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5027 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5157 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5177 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1481 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1497 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18497 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
18839 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
19133 if (DCI.isBeforeLegalizeOps()) in tryToReplaceScalarFPConversionWithSVE()
19584 if (DCI.isBeforeLegalizeOps()) in performSVEAndCombine()
20122 if (DCI.isBeforeLegalizeOps()) in performConcatVectorsCombine()
20239 if (DCI.isBeforeLegalizeOps()) in performExtractSubvectorCombine()
20312 if (DCI.isBeforeLegalizeOps()) in tryCombineFixedPointConvert()
20749 if (DCI.isBeforeLegalizeOps()) in performAddSubLongCombine()
21531 if (DCI.isBeforeLegalizeOps()) in tryCombineLongOpWithDup()
22581 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND && in performExtendCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp4381 if (DCI.isBeforeLegalizeOps()) in performANDCombine()
4475 if (DCI.isBeforeLegalizeOps()) in performSRLCombine()
4651 if (!DCI.isBeforeLegalizeOps()) in performBITCASTCombine()
4738 if (DCI.isBeforeLegalizeOps()) in performORCombine()
5112 if (DCI.isBeforeLegalizeOps()) in performBITREV_WCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1871 if (DCI.isBeforeLegalizeOps() || in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp5464 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
H A DSIISelLowering.cpp7233 if (DCI.isBeforeLegalizeOps() || in promoteUniformOpToI32()
13163 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps()) in performOrCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp42548 if (!DCI.isBeforeLegalizeOps() && N0.hasOneUse()) { in combineTargetShuffle()
45483 if (!DCI.isBeforeLegalizeOps()) in combineCastedMaskArithmetic()
46525 if (DCI.isBeforeLegalizeOps()) in combineExtractWithShuffle()
47206 if (!DCI.isBeforeLegalizeOps()) in combineToExtendBoolVectorInReg()
47464 !DCI.isBeforeLegalizeOps()); in combineVSelectToBLENDV()
47615 if (DCI.isBeforeLegalizeOps()) in combineSelect()
49128 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
50983 if (N0.getOpcode() == ISD::BITCAST && !DCI.isBeforeLegalizeOps()) { in convertIntLogicToFPLogic()
51739 if (DCI.isBeforeLegalizeOps()) in combineAnd()
52457 if (DCI.isBeforeLegalizeOps()) in combineOr()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4391 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } in isBeforeLegalizeOps() function
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3519 if (DCI.isBeforeLegalizeOps()) in PerformDAGCombine()
H A DHexagonISelLoweringHVX.cpp3636 if (DCI.isBeforeLegalizeOps()) in PerformHvxDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16063 if (DCI.isBeforeLegalizeOps()) in expandVSXLoadForLE()
16129 if (DCI.isBeforeLegalizeOps()) in expandVSXStoreForLE()
19133 bool LegalOps = !DCI.isBeforeLegalizeOps(); in combineFMALike()