Lines Matching refs:isBeforeLegalizeOps
624 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
640 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
2980 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
4045 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
4482 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4491 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4755 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4811 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4941 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4961 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4977 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4995 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
5080 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
5204 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5265 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
6708 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareUREMEqFold()
6842 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) in prepareUREMEqFold()
6857 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareUREMEqFold()
6967 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareSREMEqFold()
7127 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) in prepareSREMEqFold()
7139 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareSREMEqFold()