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Searched refs:isBeforeLegalize (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1509 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1525 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1685 if (!DCI.isBeforeLegalize() || in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2813 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performBitcastCombine()
2848 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performSETCCCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3799 if (!DCI.isBeforeLegalize()) in performLoadCombine()
3852 if (!DCI.isBeforeLegalize()) in performStoreCombine()
5230 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
H A DSIISelLowering.cpp11506 if (DCI.isBeforeLegalize()) in performAndCombine()
13398 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine()
13449 if (!DCI.isBeforeLegalize()) in performExtractVectorEltCombine()
14792 if (!DCI.isBeforeLegalize()) { in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp19022 if (!DCI.isBeforeLegalize() && in performANDSETCCCombine()
19176 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performFirstTrueTestVectorCombine()
19206 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performLastTrueTestVectorCombine()
20996 if (DCI.isBeforeLegalize()) in tryConvertSVEWideCompare()
21181 if (DCI.isBeforeLegalize()) in tryCombineWhileLo()
22547 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in performTBISimplification()
23152 if (!DCI.isBeforeLegalize()) in performMaskedGatherScatterCombine()
23188 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in performNEONPostLDSTCombine()
23864 if (DCI.isBeforeLegalize() && in performVecReduceBitwiseCombine()
23926 if (DCI.isBeforeLegalize() && VT.isScalarInteger() && in performSETCCCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp623 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
639 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
2979 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts()
4560 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
4647 if (DCI.isBeforeLegalize() && in SimplifySetCC()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4223 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } in isBeforeLegalize() function
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12728 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineBUILD_VECTORToVPADDL()
13536 if (DCI.isBeforeLegalize()) return SDValue(); in PerformADDECombine()
13918 if (DCI.isBeforeLegalize()) in PerformSHLSimplify()
14226 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMULCombine()
14304 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in CombineANDShift()
16247 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformVLDCombine()
16255 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMVEVLDCombine()
17730 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformShiftCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp13433 if (!DCI.isBeforeLegalize() && !DCI.isCalledByLegalizer()) in performADDCombine()
13875 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in expandMul()
14987 if (DCI.isBeforeLegalize()) in combineBinOp_VLToVWBinOp_VL()
16361 if (!DCI.isBeforeLegalize()) in legalizeScatterGatherIndexType()
17351 if (DCI.isBeforeLegalize() && IsScalarizable && in PerformDAGCombine()
17380 L && DCI.isBeforeLegalize() && IsScalarizable && L->isSimple() && in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp43875 if (DCI.isBeforeLegalize()) { in combineBitcast()
45346 if (DCI.isBeforeLegalize() && TLI.isTypeLegal(TruncSVT)) { in combineExtractVectorElt()
45729 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV()
46327 (DCI.isBeforeLegalize() || (VT != MVT::v64i1 || Subtarget.is64Bit()))) { in combineSelect()
46329 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(IntVT)) { in combineSelect()
46356 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() && in combineSelect()
47364 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
47876 if (DCI.isBeforeLegalize() && VT.isVector()) in combineMul()
47888 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in combineMul()
50300 if (DCI.isBeforeLegalize() || !Subtarget.getTargetLowering()->isCtlzFast()) in combineOrCmpEqZeroToCtlzSrl()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15057 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector()
15914 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
16364 if (!DCI.isBeforeLegalize() || !Is64BitBswapOn64BitTgt || in PerformDAGCombine()