Home
last modified time | relevance | path

Searched refs:isBeforeLegalize (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1480 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1496 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1656 if (!DCI.isBeforeLegalize() || in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp3222 if (!(DCI.isBeforeLegalize() && VT.isScalarInteger() && in performBitcastCombine()
3364 if (!DCI.isBeforeLegalize()) in performSETCCCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3867 if (!DCI.isBeforeLegalize()) in performLoadCombine()
3920 if (!DCI.isBeforeLegalize()) in performStoreCombine()
5463 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
H A DSIISelLowering.cpp12278 if (DCI.isBeforeLegalize()) in performAndCombine()
14211 if (Vec.hasOneUse() && DCI.isBeforeLegalize() && VecEltVT == ResVT) { in performExtractVectorEltCombine()
14262 if (!DCI.isBeforeLegalize()) in performExtractVectorEltCombine()
15820 if (!DCI.isBeforeLegalize()) { in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18191 if (DCI.isBeforeLegalize()) in performActiveLaneMaskCombine()
19665 if (!DCI.isBeforeLegalize() && in performANDSETCCCombine()
19819 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performFirstTrueTestVectorCombine()
19849 if (!Subtarget->hasSVE() || DCI.isBeforeLegalize()) in performLastTrueTestVectorCombine()
19885 if (DCI.isBeforeLegalize() || Idx.getOpcode() != ISD::VECTOR_FIND_LAST_ACTIVE) in performExtractLastActiveCombine()
21736 if (DCI.isBeforeLegalize()) in tryConvertSVEWideCompare()
23582 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in performTBISimplification()
24303 if (!DCI.isBeforeLegalize()) in performMaskedGatherScatterCombine()
24346 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in performNEONPostLDSTCombine()
25241 if (DCI.isBeforeLegalize() && in performVecReduceBitwiseCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp650 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
666 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits()
3108 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts()
4773 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
4860 if (DCI.isBeforeLegalize() && in SimplifySetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12795 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineBUILD_VECTORToVPADDL()
13603 if (DCI.isBeforeLegalize()) return SDValue(); in PerformADDECombine()
13995 if (DCI.isBeforeLegalize()) in PerformSHLSimplify()
14303 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMULCombine()
14381 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in CombineANDShift()
16326 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformVLDCombine()
16334 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMVEVLDCombine()
17808 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformShiftCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4390 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } in isBeforeLegalize() function
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp45708 if (DCI.isBeforeLegalize()) { in combineBitcast()
46765 if (DCI.isBeforeLegalize() && Vec.getOpcode() == ISD::VSELECT && in scalarizeExtEltFP()
47188 if (DCI.isBeforeLegalize() && TLI.isTypeLegal(TruncSVT)) { in combineExtractVectorElt()
47463 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV()
48079 (DCI.isBeforeLegalize() || (VT != MVT::v64i1 || Subtarget.is64Bit()))) { in combineSelect()
48081 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(IntVT)) { in combineSelect()
48108 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() && in combineSelect()
49128 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
49647 if (DCI.isBeforeLegalize() && VT.isVector()) in combineMul()
49677 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in combineMul()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp15392 if (!DCI.isBeforeLegalize() && !DCI.isCalledByLegalizer()) { in performADDCombine()
16005 (!DCI.isBeforeLegalize() && !DCI.isCalledByLegalizer()) || in expandMul()
17320 if (DCI.isBeforeLegalize()) in combineOp_VLToVWOp_VL()
19213 if (!DCI.isBeforeLegalize()) in legalizeScatterGatherIndexType()
20396 if (DCI.isBeforeLegalize() && IsScalarizable && in PerformDAGCombine()
20425 L && DCI.isBeforeLegalize() && IsScalarizable && L->isSimple() && in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15890 if (Subtarget.hasP9Altivec() && !DCI.isBeforeLegalize()) { in DAGCombineBuildVector()
16804 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
17257 if (!DCI.isBeforeLegalize() || !Is64BitBswapOn64BitTgt || in PerformDAGCombine()