Lines Matching refs:isBeforeLegalize
43875 if (DCI.isBeforeLegalize()) { in combineBitcast()
45346 if (DCI.isBeforeLegalize() && TLI.isTypeLegal(TruncSVT)) { in combineExtractVectorElt()
45729 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV()
46327 (DCI.isBeforeLegalize() || (VT != MVT::v64i1 || Subtarget.is64Bit()))) { in combineSelect()
46329 if (DCI.isBeforeLegalize() || TLI.isTypeLegal(IntVT)) { in combineSelect()
46356 if (DCI.isBeforeLegalize() && !Subtarget.hasAVX512() && in combineSelect()
47364 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
47876 if (DCI.isBeforeLegalize() && VT.isVector()) in combineMul()
47888 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in combineMul()
50300 if (DCI.isBeforeLegalize() || !Subtarget.getTargetLowering()->isCtlzFast()) in combineOrCmpEqZeroToCtlzSrl()
51261 RegVT.getScalarType() == MVT::i1 && DCI.isBeforeLegalize()) { in combineLoad()
51655 if (!DCI.isBeforeLegalize() && VT == MVT::v64i1 && !Subtarget.is64Bit()) { in combineStore()
53142 (DCI.isBeforeLegalize() || in combineBITREVERSE()
54268 isa<ConstantSDNode>(RHS) && !DCI.isBeforeLegalize()) { in combineSetCC()
54677 if (DCI.isBeforeLegalize()) { in combineGatherScatter()
55031 if (DCI.isBeforeLegalize() || TruncVT != MVT::v2i32) { in combineSIntToFP()