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Searched refs:isAllocatable (Results 1 – 25 of 41) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td334 let isAllocatable = 0;
341 let isAllocatable = 0;
348 let isAllocatable = 0;
364 let isAllocatable = 0;
422 let isAllocatable = 0;
430 let isAllocatable = 0;
594 let isAllocatable = 0;
662 let isAllocatable = 0;
723 let isAllocatable = 0;
731 let isAllocatable = 0;
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H A DGCNRewritePartialRegUses.cpp198 if (RC->isAllocatable() && TRI->isRegClassAligned(RC, AlignNumBits)) in getAllocatableAndAlignedRegClassMask()
224 << (SubRegRC->isAllocatable() ? "" : " not alloc") in getRegClassWithShiftedSubregs()
229 assert(SubRegRC->isAllocatable()); in getRegClassWithShiftedSubregs()
268 assert(MinRC->isAllocatable() && TRI->isRegClassAligned(MinRC, RCAlign)); in getRegClassWithShiftedSubregs()
H A DR600RegisterInfo.td163 let isAllocatable = 0 in {
209 } // End isAllocatable = 0
H A DGCNNSAReassign.cpp136 if (!MRI->isAllocatable(Reg)) in canAssign()
H A DSIFrameLowering.cpp420 MRI.isAllocatable(Reg) && !TRI->isSubRegisterEq(Reg, GITPtrLoReg)) { in emitEntryFunctionFlatScratchInit()
579 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg) && in getEntryFunctionReservedScratchRsrcReg()
675 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg) && in emitEntryFunctionPrologue()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp192 if (!RC || RC->isAllocatable()) in getAllocatableClass()
198 if (SubRC->isAllocatable()) in getAllocatableClass()
285 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
301 if (C->isAllocatable()) in getAllocatableSet()
H A DMachineRegisterInfo.cpp59 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
159 assert(RegClass->isAllocatable() && in createVirtualRegister()
543 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
H A DCalcSpillWeights.cpp292 if (HintReg && (HintReg.isVirtual() || MRI.isAllocatable(HintReg))) in weightCalcHelper()
H A DAggressiveAntiDepBreaker.cpp631 if (!MRI.isAllocatable(NewSuperReg)) continue; in FindSuitableFreeRegisters()
836 if (!MRI.isAllocatable(AntiDepReg)) { in BreakAntiDependencies()
H A DCriticalAntiDepBreaker.cpp561 if (!MRI.isAllocatable(AntiDepReg)) in BreakAntiDependencies()
H A DRegisterPressure.cpp518 } else if (MRI.isAllocatable(Reg)) { in pushReg()
553 } else if (MRI.isAllocatable(Reg)) { in pushRegLanes()
H A DRegAllocFast.cpp921 if (Hint0.isPhysical() && MRI->isAllocatable(Hint0) && RC.contains(Hint0) && in allocVirtReg()
939 if (Hint1.isPhysical() && MRI->isAllocatable(Hint1) && RC.contains(Hint1) && in allocVirtReg()
H A DMachineCSE.cpp350 if (MRI->isAllocatable(PhysDef.second) || MRI->isReserved(PhysDef.second)) in PhysRegDefsReach()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td558 let Size = 32, isAllocatable = 0 in
569 let isAllocatable = 0 in
572 let Size = 64, isAllocatable = 0 in
577 let Size = 32, isAllocatable = 0 in
587 let Size = 64, isAllocatable = 0 in
596 let Size = 32, isAllocatable = 0 in
615 let Size = 64, isAllocatable = 0 in
632 let isAllocatable = 0 in
638 let Size = 32, isAllocatable = 0 in
H A DHexagonBlockRanges.cpp224 if (RC->isAllocatable()) in HexagonBlockRanges()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td57 let isAllocatable = 0;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td62 let isAllocatable = 0;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td562 let isAllocatable = 0 in
574 let isAllocatable = 0 in
765 let isAllocatable = 0;
772 let isAllocatable = 0;
789 let isAllocatable = 0;
793 let isAllocatable = 0;
797 let isAllocatable = 0;
869 let isAllocatable = 1 in
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td195 let isAllocatable = false in
223 let isAllocatable = false, RegInfos = GRLenRI in
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td46 let isAllocatable = allocatable in
348 let isAllocatable = 0, CopyCost = -1 in
355 let isAllocatable = 0 in
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td170 let isAllocatable = 0, CopyCost = -1 in {
326 let isAllocatable = 0 in
481 let isAllocatable = 0;
484 let isAllocatable = 0;
488 let isAllocatable = 0;
491 let isAllocatable = 0;
497 let isAllocatable = 0;
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h119 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td294 let isAllocatable = 0;
345 let isAllocatable = 0;
406 let isAllocatable = 0;
424 let isAllocatable = 0;
481 let isAllocatable = 0;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td150 let isAllocatable = 0 in {
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h101 bool isAllocatable() const { return Allocatable; } in isAllocatable() function

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