| /freebsd/sys/contrib/dev/mediatek/mt76/ |
| H A D | mmio.c | 90 dev->mmio.irqmask &= ~clear; in mt76_set_irq_mask()
91 dev->mmio.irqmask |= set; in mt76_set_irq_mask()
95 dev->mmio.irqmask); in mt76_set_irq_mask()
97 mt76_mmio_wr(dev, addr, dev->mmio.irqmask); in mt76_set_irq_mask()
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| H A D | mt76x02_mmio.c | 257 intr &= dev->mt76.mmio.irqmask; in mt76x02_irq_handler()
263 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt76x02_irq_handler()
428 u32 mask = dev->mt76.mmio.irqmask; in mt76x02_watchdog_reset()
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| H A D | mt792x_dma.c | 38 intr &= dev->mt76.mmio.irqmask; in mt792x_irq_tasklet()
41 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt792x_irq_tasklet()
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| H A D | mt76.h | 607 u32 irqmask; member
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7996/ |
| H A D | mmio.c | 244 mdev->mmio.irqmask &= ~clear; in mt7996_dual_hif_set_irq_mask()
245 mdev->mmio.irqmask |= set; in mt7996_dual_hif_set_irq_mask()
248 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); in mt7996_dual_hif_set_irq_mask()
249 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); in mt7996_dual_hif_set_irq_mask()
274 intr &= dev->mt76.mmio.irqmask; in mt7996_irq_tasklet()
279 intr1 &= dev->mt76.mmio.irqmask; in mt7996_irq_tasklet()
285 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7996_irq_tasklet()
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| H A D | mac.c | 1664 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); in mt7996_mac_restart()
1667 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); in mt7996_mac_restart()
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7603/ |
| H A D | core.c | 24 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7603_irq_handler()
26 intr &= dev->mt76.mmio.irqmask; in mt7603_irq_handler()
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| H A D | mac.c | 1425 u32 mask = dev->mt76.mmio.irqmask; in mt7603_mac_watchdog_reset()
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7915/ |
| H A D | mmio.c | 872 mdev->mmio.irqmask &= ~clear; in mt7915_dual_hif_set_irq_mask()
873 mdev->mmio.irqmask |= set; in mt7915_dual_hif_set_irq_mask()
878 mdev->mmio.irqmask); in mt7915_dual_hif_set_irq_mask()
880 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); in mt7915_dual_hif_set_irq_mask()
881 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); in mt7915_dual_hif_set_irq_mask()
906 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); in mt7915_irq_tasklet()
913 intr &= dev->mt76.mmio.irqmask; in mt7915_irq_tasklet()
919 intr1 &= dev->mt76.mmio.irqmask; in mt7915_irq_tasklet()
925 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7915_irq_tasklet()
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| H A D | mac.c | 1410 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); in mt7915_mac_restart()
1414 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); in mt7915_mac_restart()
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| /freebsd/sys/contrib/dev/mediatek/mt76/mt7615/ |
| H A D | mmio.c | 95 intr &= dev->mt76.mmio.irqmask; in mt7615_irq_tasklet()
98 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); in mt7615_irq_tasklet()
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| /freebsd/usr.sbin/dumpcis/ |
| H A D | cardinfo.h | 147 int irqmask; /* Interrupt number(s) to allocate */ member
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| /freebsd/sys/i386/pci/ |
| H A D | pci_pir.c | 84 static int pci_pir_choose_irq(struct pci_link *pci_link, int irqmask);
565 pci_pir_choose_irq(struct pci_link *pci_link, int irqmask) in pci_pir_choose_irq() argument
570 realmask = pci_link->pl_irqmask & irqmask; in pci_pir_choose_irq()
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| /freebsd/sys/dev/pccard/ |
| H A D | pccardvarp.h | 72 uint16_t irqmask; member
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| /freebsd/sys/dev/sound/pci/ |
| H A D | emu10kx-pcm.c | 76 uint32_t irqmask; member
874 ch->irqmask = EMU_INTE_ADCBUFENABLE; in emurchan_init()
982 ch->ihandle = emu_intr_register(sc->card, ch->irqmask, ch->iprmask, &emu_pcm_intr, sc); in emurchan_trigger()
1052 ch->irqmask = EMU_INTE_EFXBUFENABLE; in emufxrchan_init()
1136 ch->ihandle = emu_intr_register(sc->card, ch->irqmask, ch->iprmask, &emu_pcm_intr, sc); in emufxrchan_trigger()
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| H A D | emu10k1.c | 202 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask; member
964 ch->irqmask = EMU_INTE_ADCBUFENABLE; in emurchan_init()
972 ch->irqmask = EMU_INTE_EFXBUFENABLE; in emurchan_init()
980 ch->irqmask = EMU_INTE_MICBUFENABLE; in emurchan_init()
1094 val |= ch->irqmask; in emurchan_trigger()
1105 val &= ~ch->irqmask; in emurchan_trigger()
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