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/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h25 static inline uint32_t DecodeImmShift(const uint32_t type, const uint32_t imm5, in DecodeImmShift() argument
33 return imm5; in DecodeImmShift()
36 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
39 return (imm5 == 0 ? 32 : imm5); in DecodeImmShift()
41 if (imm5 == 0) { in DecodeImmShift()
46 return imm5; in DecodeImmShift()
70 const uint32_t imm5) { in DecodeImmShift() argument
72 return DecodeImmShift(shift_t, imm5, dont_care); in DecodeImmShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrFormats.td78 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5),
79 deriveInsnMnemonic<NAME>.ret, "$rj, $imm5"> {
80 bits<5> imm5;
84 let Inst{14-10} = imm5;
91 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5, uimm4:$imm4),
92 deriveInsnMnemonic<NAME>.ret, "$rj, $imm5, $imm4"> {
93 bits<5> imm5;
98 let Inst{14-10} = imm5;
106 : LAInst<(outs GPR:$rd), (ins uimm5:$imm5, uimm8:$imm8),
107 deriveInsnMnemonic<NAME>.ret, "$rd, $imm5, $imm8"> {
[all …]
H A DLoongArchInstrFormats.td116 bits<5> imm5;
121 let Inst{14-10} = imm5;
304 bits<5> imm5;
309 let Inst{4-0} = imm5;
318 bits<5> imm5;
323 let Inst{4-0} = imm5;
H A DLoongArchLASXInstrFormats.td218 bits<5> imm5;
223 let Inst{14-10} = imm5;
329 bits<5> imm5;
335 let Inst{22-18} = imm5;
H A DLoongArchLSXInstrFormats.td246 bits<5> imm5;
251 let Inst{14-10} = imm5;
H A DLoongArchInstrInfo.td646 : Fmt2RI5<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm5),
647 "$rd, $rj, $imm5">;
846 def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12),
847 "$imm5, $rj, $imm12">;
961 def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk),
962 "$imm5, $rj, $rk">;
H A DLoongArchLASXInstrInfo.td95 : Fmt2RI5_XXI<op, (outs LASX256:$xd), (ins LASX256:$xj, ImmOpnd:$imm5),
96 "$xd, $xj, $imm5">;
124 (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm5),
125 "$xd, $rj, $imm8, $imm5">;
160 : Fmt2RI5_XXI<op, (outs LASX256:$dst), (ins LASX256:$xd, LASX256:$xj, ImmOpnd:$imm5),
161 "$xd, $xj, $imm5">;
H A DLoongArchLSXInstrInfo.td253 : Fmt2RI5_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm5),
254 "$vd, $vj, $imm5">;
317 : Fmt2RI5_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm5),
318 "$vd, $vj, $imm5">;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td138 !strconcat(opstr, "\t$rz, $imm5"), []> {
140 bits<5> imm5;
145 let Inst{4 - 0} = imm5;
149 AddrModeNone, (outs CARRY:$ca), (ins mGPR:$rx, Immoperand:$imm5),
150 !strconcat(opstr, "\t$rx, $imm5"), []> {
152 bits<5> imm5;
157 let Inst{4 - 0} = imm5;
173 AddrModeNone, (outs mGPR:$rz), (ins mGPR:$rx, uimm5:$imm5),
174 !strconcat(opstr, "\t$rz, $rx, $imm5"), [(set mGPR:$rz, (opnode mGPR:$rx, uimm5:$imm5))]> {
177 bits<5> imm5;
[all …]
H A DCSKYInstrFormats.td267 (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
268 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
271 bits<5> imm5;
276 let Inst{4 - 0} = imm5;
286 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
287 bits<5> imm5;
290 let Inst{25 - 21} = imm5;
397 let Inst{4 - 0} = regs{4 - 0}; // imm5
474 (outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
475 !strconcat(op, "\t$rx, $imm5"), pattern> {
[all …]
H A DCSKYInstrInfo.td533 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
534 [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
536 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
537 [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
539 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
540 [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
542 (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
543 [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
545 def ROTRI32 : CSKYPseudo<(outs GPR:$rz), (ins GPR:$rx, oimm5:$imm5),
546 "rotri32 $rz, $rx, $imm5", []>;
[all...]
H A DCSKYInstrInfo16Instr.td162 def CMPLEI16 : CSKYPseudo<(outs CARRY:$ca), (ins mGPR:$rx, uimm5:$imm5),
163 "cmplei16\t$rx, $imm5", []>;
313 def BCLRI16 : I16_Z_5<0b100, (outs mGPR:$rz), (ins mGPR:$rZ, uimm5:$imm5),
315 def BSETI16 : I16_Z_5<0b101, (outs mGPR:$rz), (ins mGPR:$rZ, uimm5:$imm5),
320 def BTSTI16 : I16_Z_5<0b110, (outs CARRY:$ca), (ins mGPR:$rz, uimm5:$imm5),
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZimop.td14 class RVInstIMopr<bits<7> imm7, bits<5> imm5, bits<3> funct3, RISCVOpcode opcode,
18 let Inst{30} = imm5{4};
20 let Inst{27-26} = imm5{3-2};
22 let Inst{21-20} = imm5{1-0};
44 class RVMopr<bits<7> imm7, bits<5> imm5, bits<3> funct3,
46 : RVInstIMopr<imm7, imm5, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
H A DRISCVInstrInfoXCV.td82 "$rd, $rs1, $rs2, $imm5"> {
83 bits<5> imm5;
86 let Inst{29-25} = imm5;
92 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
96 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
167 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
168 "$rd, $rs1, $rs2, $imm5"> {
169 bits<5> imm5;
172 let Inst{29-25} = imm5;
185 (ins GPR:$rs1, uimm5:$imm5), opcodest
[all...]
H A DRISCVInstrFormatsC.td296 bits<5> imm5;
301 let Inst{12-10} = imm5{4-2};
303 let Inst{6-5} = imm5{1-0};
315 bits<5> imm5;
320 let Inst{12-10} = imm5{4-2};
322 let Inst{6-5} = imm5{1-0};
H A DRISCVInstrInfoC.td783 uimm5:$imm5),
784 "$opcode, $funct3, $rd, ${imm5}(${rs1})">;
789 uimm5:$imm5),
790 "$opcode, $funct3, $rs2, ${imm5}(${rs1})">;
829 def : InstAlias<".insn_cl $opcode, $funct3, $rd, ${imm5}(${rs1})",
831 AnyRegC:$rs1, uimm5:$imm5)>;
835 def : InstAlias<".insn_cs $opcode, $funct3, $rs2, ${imm5}(${rs1})",
837 AnyRegC:$rs1, uimm5:$imm5)>;
H A DRISCVInstrInfoVVLPatterns.td2449 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.RegClass:$passthru, (ImmPat simm5:$imm5),
2452 vti.RegClass:$passthru, simm5:$imm5, GPR:$vl, vti.Log2SEW, TU_MU)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb.td239 // t_addrmode_is4 := reg + imm5 * 4
251 // t_addrmode_is2 := reg + imm5 * 2
263 // t_addrmode_is1 := reg + imm5
716 // Loads: reg/reg and reg/imm5
726 def i : // reg/imm5
738 // Stores: reg/reg and reg/imm5
744 def i : // reg/imm5
1079 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1081 "asr", "\t$Rd, $Rm, $imm5",
1082 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
[all …]
H A DARMInstrFormats.td1334 let Inst{10-6} = addr{7-3}; // imm5
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td5212 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
5213 asm, "\t$Pd, $Pg/z, $Zn, $imm5",
5219 bits<5> imm5;
5223 let Inst{20-16} = imm5;
5663 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
5664 asm, "\t$Zd, $imm5, $imm5b",
5667 bits<5> imm5;
5674 let Inst{9-5} = imm5;
5698 …(add (nxv16i8 (step_vector_oneuse simm5_8b_tgt:$imm5b)), (nxv16i8 (splat_vector(simm5_8b:$imm5)))),
5699 … (!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, (!cast<SDNodeXForm>("trunc_imm") $imm5b))>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td228 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
237 bits<5> imm5;
244 let Inst{4-0} = imm5;
H A DMips64InstrInfo.td926 def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
928 (SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
932 def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
934 (SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
938 def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
940 (SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/MIPS/
H A DEmulateInstructionMIPS.cpp1490 uint32_t imm5 = insn.getOperand(2).getImm(); in Emulate_SWSP() local
1510 address = address + imm5; in Emulate_SWSP()
1635 uint32_t imm5 = insn.getOperand(2).getImm(); in Emulate_LWSP() local
1647 base_address = base_address + imm5; in Emulate_LWSP()
1738 int32_t imm5 = insn.getOperand(0).getImm(); in Emulate_JRADDIUSP() local
1757 int32_t result = src_opd_val + imm5; in Emulate_JRADDIUSP()
1769 context.SetRegisterPlusOffset(*reg_info_sp, imm5); in Emulate_JRADDIUSP()
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp354 uint16_t imm5 = extractBits(val, 5, 5) << 2; in relocate() local
355 insn |= imm8 | imm4_3 | imm7_6 | imm2_1 | imm5; in relocate()
372 uint16_t imm5 = extractBits(val, 5, 5) << 2; in relocate() local
373 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp3755 uint32_t imm5; // encoding for the shift amount in EmulateShiftImm() local
3774 imm5 = Bits32(opcode, 10, 6); in EmulateShiftImm()
3785 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); in EmulateShiftImm()
3793 imm5 = Bits32(opcode, 11, 7); in EmulateShiftImm()
3800 if (shift_type == SRType_ROR && imm5 == 0) in EmulateShiftImm()
3810 (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); in EmulateShiftImm()
5373 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateSTRRegister() local
5374 shift_n = DecodeImmShift(typ, imm5, shift_t); in EmulateSTRRegister()
6558 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRRegister() local
6559 shift_n = DecodeImmShift(type, imm5, shift_t); in EmulateLDRRegister()
[all …]

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