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Searched refs:imm3 (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZimop.td25 class RVInstRMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3, RISCVOpcode opcode,
29 let Inst{30} = imm3{2};
31 let Inst{27-26} = imm3{1-0};
50 class RVMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3,
52 : RVInstRMoprr<imm4, imm3, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
H A DRISCVInstrInfoZcmop.td15 class CMOPInst<bits<3> imm3, string opcodestr>
19 let Inst{10-8} = imm3;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrFormats.td39 : LAInst<(outs), (ins GPR:$rj, uimm3:$imm3),
40 deriveInsnMnemonic<NAME>.ret, "$rj, $imm3"> {
41 bits<3> imm3;
45 let Inst{12-10} = imm3;
175 : LAInst<(outs GPR:$rd), (ins GPR:$rj, uimm3:$imm3),
176 deriveInsnMnemonic<NAME>.ret, "$rd, $rj, $imm3"> {
177 bits<3> imm3;
182 let Inst{12-10} = imm3;
H A DLoongArchLASXInstrFormats.td132 bits<3> imm3;
137 let Inst{12-10} = imm3;
146 bits<3> imm3;
151 let Inst{12-10} = imm3;
160 bits<3> imm3;
165 let Inst{12-10} = imm3;
295 bits<3> imm3;
301 let Inst{20-18} = imm3;
H A DLoongArchLSXInstrFormats.td160 bits<3> imm3;
165 let Inst{12-10} = imm3;
174 bits<3> imm3;
179 let Inst{12-10} = imm3;
188 bits<3> imm3;
193 let Inst{12-10} = imm3;
340 bits<3> imm3;
346 let Inst{20-18} = imm3;
H A DLoongArchInstrFormats.td99 bits<3> imm3;
105 let Inst{17-15} = imm3;
H A DLoongArchLASXInstrInfo.td75 : Fmt2RI3_XXI<op, (outs LASX256:$xd), (ins LASX256:$xj, ImmOpnd:$imm3),
76 "$xd, $xj, $imm3">;
79 : Fmt2RI3_RXI<op, (outs GPR:$rd), (ins LASX256:$xj, ImmOpnd:$imm3),
80 "$rd, $xj, $imm3">;
114 (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3),
115 "$xd, $rj, $imm8, $imm3">;
146 : Fmt2RI3_XXI<op, (outs LASX256:$dst), (ins LASX256:$xd, LASX256:$xj, ImmOpnd:$imm3),
147 "$xd, $xj, $imm3">;
153 : Fmt2RI3_XRI<op, (outs LASX256:$dst), (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm3),
154 "$xd, $rj, $imm3">;
H A DLoongArchLSXInstrInfo.td237 : Fmt2RI3_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm3),
238 "$vd, $vj, $imm3">;
241 : Fmt2RI3_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm3),
242 "$rd, $vj, $imm3">;
277 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm3),
278 "$vd, $rj, $imm8, $imm3">;
307 : Fmt2RI3_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm3),
308 "$vd, $rj, $imm3">;
H A DLoongArchInstrInfo.td643 : Fmt3RI3<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm3),
644 "$rd, $rj, $rk, $imm3">;
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h308 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbExpandImm_C() local
310 const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh; in ThumbExpandImm_C()
353 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbImm12() local
355 const uint32_t imm12 = i << 11 | imm3 << 8 | imm8; in ThumbImm12()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSMEInstrFormats.td72 …Pseudo<(outs), (ins MatrixIndexGPR32Op8_11:$Rv, index_ty:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm), …
80 …Pseudo<(outs), (ins MatrixIndexGPR32Op8_11:$Rv, index_ty:$imm3, multi_vector_ty:$Zn, multi_vector_…
88 …Pseudo<(outs), (ins MatrixIndexGPR32Op8_11:$Rv, index_ty:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm, i…
124 Pseudo<(outs multi_vector_ty:$Zd), (ins MatrixIndexGPR32Op8_11:$Rv, index_ty:$imm3), []> {
1433 sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm),
1434 mnemonic,"\t$ZAd[$Rv, $imm3, " # !if(op{5}, "vgx4", "vgx2") # "], $Zn, $Zm",
1439 bits<3> imm3;
1450 let Inst{2-0} = imm3;
1460 def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
1461 …ction>(NAME) matrix_ty:$ZAd, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, multi_vector_ty:$Z…
[all …]
H A DSVEInstrFormats.td2179 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, timm32_0_7:$imm3),
2180 asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
2185 bits<3> imm3;
2189 let Inst{18-16} = imm3;
4066 let Inst{18-16} = imm{2-0}; // imm3
4108 let Inst{18-16} = imm{2-0}; // imm3
4170 let Inst{18-16} = imm{2-0}; // imm3
4314 let Inst{18-16} = imm{2-0}; // imm3
4354 let Inst{18-16} = imm{2-0}; // imm3
4948 let Inst{18-16} = imm{2-0}; // imm3
[all …]
H A DAArch64InstrFormats.td1292 // {2-0} - imm3
12545 // Base CPA scalar add/subtract with lsl #imm3 shift
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb.td976 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
978 "add", "\t$Rd, $Rm, $imm3",
979 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
981 bits<3> imm3;
982 let Inst{8-6} = imm3;
1015 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1018 imm0_7:$imm3))]>,
1320 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1322 "sub", "\t$Rd, $Rm, $imm3",
1323 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
[all …]
H A DARMInstrThumb2.td762 let Inst{14-12} = 0b000; // imm3
848 let Inst{14-12} = 0b000; // imm3
1005 let Inst{14-12} = 0b000; // imm3
1047 let Inst{14-12} = 0b000; // imm3
1164 let Inst{14-12} = 0b000; // imm3
2982 let Inst{14-12} = 0b000; // imm3
3498 let Inst{14-12} = 0b000; // imm3
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td528 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1408 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateMOVRdImm() local
1411 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; in EmulateMOVRdImm()
1893 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDSPImm() local
1895 imm32 = (i << 11) | (imm3 << 8) | imm8; in EmulateADDSPImm()
3082 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDImmThumb() local
3084 imm32 = (i << 11) | (imm3 << 8) | imm8; in EmulateADDImmThumb()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td1605 def imm3 : NVPTXInst<(outs regclass:$dst),