| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterBankInfo.cpp | |
| H A D | X86DomainReassignment.cpp | 45 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
61 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
63 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
65 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
67 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
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| H A D | X86InstrInfo.cpp | 4178 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
4179 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
4180 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
4425 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()
4429 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4433 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4436 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
4439 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4441 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4448 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 224 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
226 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
228 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
230 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
232 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
234 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
236 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
238 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
240 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
253 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
[all …]
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| H A D | Mips16InstrInfo.cpp | 115 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
132 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.cpp | 408 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
410 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
413 } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
415 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
417 else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
419 else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
450 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
452 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
455 } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
457 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.cpp | 122 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
126 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
128 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
130 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
132 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
134 else if (LoongArch::CFRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
161 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
165 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
167 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
169 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 653 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
656 } else if (RISCV::GPRF16RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
658 } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
660 } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
662 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
664 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
666 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
668 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
670 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
672 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1547 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1548 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1549 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1550 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1578 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
1579 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
1581 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1582 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1880 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1881 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
[all …]
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| H A D | PPCVSXCopy.cpp | 44 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 700 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); in canFoldIntoCSel()
786 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
787 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in canInsertSelect()
800 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
801 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
1381 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) && in UpdateOperandRegClass()
5485 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
5489 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
5491 else if (AArch64::PNRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
5492 AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
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| H A D | AArch64RegisterInfo.cpp | 1356 (AArch64::ZPRRegClass.hasSubClassEq(DstRC) || in shouldCoalesce()
1357 AArch64::ZPRRegClass.hasSubClassEq(SrcRC))) { in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterBank.cpp | 39 if (!RC.hasSubClassEq(&SubRC)) in verify()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 960 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
971 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
978 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
985 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
992 } else if (ARM::cl_FPSCR_NZCVRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1003 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1010 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1031 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in storeRegToStackSlot()
1047 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1059 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
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| H A D | Thumb2InstrInfo.cpp | 180 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
190 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
222 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
231 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.cpp | 555 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
558 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
592 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
595 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 127 return RC != this && hasSubClassEq(RC); in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
144 return RC->hasSubClassEq(this); in hasSuperClassEq()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.cpp | 802 if (M68k::XR16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
804 if (M68k::DR8RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
806 if (M68k::CCRCRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
810 if (M68k::XR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
340 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
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| H A D | SystemZInstrInfo.cpp | 619 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) || in canInsertSelect()
620 SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in canInsertSelect()
621 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in canInsertSelect()
646 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) { in insertSelect()
661 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in insertSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.cpp | 497 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
511 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
554 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
566 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 978 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
982 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
986 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
990 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
994 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
998 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1002 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1023 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1026 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1029 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 58 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 312 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
|