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Searched refs:hasSubClassEq (Results 1 – 25 of 47) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp51 if (X86::GR8RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
52 X86::GR16RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
53 X86::GR32RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
54 X86::GR64RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
55 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
56 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
59 if (X86::FR32XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
60 X86::FR64XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
61 X86::VR128XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
62 X86::VR256XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp
H A DX86DomainReassignment.cpp45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
H A DX86InstrInfo.cpp4119 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
4120 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
4121 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
4365 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()
4369 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4373 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4376 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
4379 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4381 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
4388 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp224 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
226 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
228 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
230 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
232 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
234 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
236 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
238 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
240 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
253 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
[all …]
H A DMips16InstrInfo.cpp116 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
135 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp118 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
122 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
124 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
126 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
128 else if (LoongArch::LASX256RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
130 else if (LoongArch::CFRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
156 if (LoongArch::GPRRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
160 else if (LoongArch::FPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
162 else if (LoongArch::FPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
164 else if (LoongArch::LSX128RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp407 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
409 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
412 } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
414 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
416 else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
418 else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
451 if (CSKY::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
453 } else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
456 } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
458 else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h135 if (RISCV::VRM8RegClass.hasSubClassEq(RC)) in getLargestSuperClass()
137 if (RISCV::VRM4RegClass.hasSubClassEq(RC)) in getLargestSuperClass()
139 if (RISCV::VRM2RegClass.hasSubClassEq(RC)) in getLargestSuperClass()
141 if (RISCV::VRRegClass.hasSubClassEq(RC)) in getLargestSuperClass()
H A DRISCVInstrInfo.cpp570 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
574 } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
577 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
580 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
583 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
586 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
588 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
590 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
592 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
594 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(R in storeRegToStackSlot()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h246 if (ARM::MQPRRegClass.hasSubClassEq(RC)) in getLargestSuperClass()
248 if (ARM::SPRRegClass.hasSubClassEq(RC)) in getLargestSuperClass()
250 if (ARM::DPR_VFP2RegClass.hasSubClassEq(RC)) in getLargestSuperClass()
252 if (ARM::GPRRegClass.hasSubClassEq(RC)) in getLargestSuperClass()
H A DARMBaseInstrInfo.cpp1132 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1143 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1150 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1157 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1168 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1175 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1196 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in storeRegToStackSlot()
1212 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1224 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1248 if (ARM::QQPRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
[all …]
H A DThumb2InstrInfo.cpp179 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
189 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
223 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
232 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp640 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); in canFoldIntoCSel()
726 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
727 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in canInsertSelect()
740 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
741 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
1267 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) && in UpdateOperandRegClass()
4847 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
4851 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
4853 else if (AArch64::PNRRegClass.hasSubClassEq(RC) || in storeRegToStackSlot()
4854 AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1549 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1550 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1551 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1552 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1580 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
1581 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
1583 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1584 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1864 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1865 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
[all …]
H A DPPCVSXCopy.cpp54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBank.cpp39 if (!RC.hasSubClassEq(&SubRC)) in verify()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp555 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
558 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
594 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
597 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp740 if (M68k::DR8RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
742 if (M68k::CCRCRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
747 assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
750 assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass"); in getLoadStoreRegOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp309 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
337 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h127 return RC != this && hasSubClassEq(RC); in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
144 return RC->hasSubClassEq(this); in hasSuperClassEq()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp497 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
511 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
556 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
568 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp973 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
977 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
981 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
985 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
989 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
993 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
997 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1020 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1023 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
1026 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()

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