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Searched refs:hasSSE1 (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Subtarget.h192 bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); } in canUseCMOV()
193 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1() function
212 return hasSSE1() || hasPRFCHW() || hasPREFETCHI(); in hasSSEPrefetch()
H A DX86InstrPredicates.td54 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
55 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
158 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
H A DX86CallingConv.td141 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
149 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
218 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
222 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
384 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,
385 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,
574 CCIfSubtarget<"hasSSE1()",
653 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,
654 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,
701 CCIfSubtarget<"hasSSE1()",
H A DX86FastISel.cpp152 (VT == MVT::f32 && Subtarget->hasSSE1()) || VT == MVT::f16; in isScalarFPTypeInSSEReg()
302 if (VT == MVT::f32 && !Subtarget->hasSSE1()) in isTypeLegal()
320 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitLoad()
482 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitStore()
1360 bool HasSSE1 = Subtarget->hasSSE1(); in X86ChooseCmpOpcode()
2165 !((Subtarget->hasSSE1() && RetVT == MVT::f32) || in X86FastEmitSSESelect()
2826 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
3007 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
3173 if (!Subtarget->hasSSE1()) in fastLowerArguments()
3538 assert((Subtarget->hasSSE1() || !NumXMMRegs) in fastLowerCall()
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H A DX86ISelLoweringCall.cpp289 if (Subtarget.hasSSE1()) in getByValTypeAlignment()
323 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) && in getOptimalMemOpType()
347 return Subtarget.hasSSE1(); in isSafeMemOpType()
807 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerReturn()
1148 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerCallResult()
1473 if (isSoftFloat || !Subtarget.hasSSE1()) in get64BitArgumentXMMs()
1555 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) && in createVarArgAreaAndStoreRegisters()
2329 (Subtarget.hasSSE1() || !M->getModuleFlag("SkipRaxSetup"))) { in LowerCall()
2344 assert((Subtarget.hasSSE1() || !NumXMMRegs) in LowerCall()
H A DX86RegisterInfo.cpp286 bool HasSSE = Subtarget.hasSSE1(); in getCalleeSavedRegs()
428 bool HasSSE = Subtarget.hasSSE1(); in getCallPreservedMask()
711 if (ST.hasSSE1() && in isArgumentRegister()
H A DX86LegalizerInfo.cpp
H A DX86TargetTransformInfo.cpp166 if (Vector && !ST->hasSSE1()) in getNumberOfRegisters()
213 if (ST->hasSSE1() && PreferVectorWidth >= 128) in getRegisterBitWidth()
1440 if (ST->hasSSE1()) in getArithmeticInstrCost()
2269 if (ST->hasSSE1()) { in getShuffleCost()
3598 if (ST->hasSSE1()) in getCmpSelInstrCost()
4717 if (ST->hasSSE1()) in getIntrinsicInstrCost()
4868 (MScalarTy == MVT::f32 && ST->hasSSE1() && Index == 0 && in getVectorInstrCost()
6330 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); in isLegalNTLoad()
6355 return ST->hasSSE1(); in isLegalNTStore()
H A DX86ISelLowering.cpp729 } else if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1() && in X86TargetLowering()
887 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) { in X86TargetLowering()
1056 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) { in X86TargetLowering()
3437 (VT == MVT::f32 && Subtarget.hasSSE1()) || VT == MVT::f16; in isScalarFPTypeInSSEReg()
3509 if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128) in hasAndNot()
23584 if ((VT == MVT::f32 && Subtarget.hasSSE1()) || in getSqrtEstimate()
23585 (VT == MVT::v4f32 && Subtarget.hasSSE1() && Reciprocal) || in getSqrtEstimate()
23635 if ((VT == MVT::f32 && Subtarget.hasSSE1()) || in getRecipEstimate()
23636 (VT == MVT::v4f32 && Subtarget.hasSSE1()) || in getRecipEstimate()
25592 assert(Subtarget.hasSSE1() && "Expected SSE"); in LowerStore()
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H A DX86InstrInfo.cpp10739 if (!ST.hasSSE1()) in buildClearRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp146 bool HasSSE1 = ST->hasSSE1(); in getPartialMappingIdx()
H A DX86LegalizerInfo.cpp37 bool HasSSE1 = Subtarget.hasSSE1(); in X86LegalizerInfo()