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Searched refs:hasSSE1 (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Subtarget.h192 bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); } in canUseCMOV()
193 bool hasSSE1() const { return X86SSELevel >= SSE1; } in hasSSE1() function
212 return hasSSE1() || hasPRFCHW() || hasPREFETCHI(); in hasSSEPrefetch()
H A DX86InstrPredicates.td53 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
54 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
153 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
H A DX86CallingConv.td141 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
149 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
222 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
226 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
396 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,
397 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,
593 CCIfSubtarget<"hasSSE1()",
674 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>,
675 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>,
722 CCIfSubtarget<"hasSSE1()",
H A DX86FastISel.cpp151 (VT == MVT::f32 && Subtarget->hasSSE1()) || VT == MVT::f16; in isScalarFPTypeInSSEReg()
301 if (VT == MVT::f32 && !Subtarget->hasSSE1()) in isTypeLegal()
319 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitLoad()
481 bool HasSSE1 = Subtarget->hasSSE1(); in X86FastEmitStore()
1361 bool HasSSE1 = Subtarget->hasSSE1(); in X86ChooseCmpOpcode()
2159 !((Subtarget->hasSSE1() && RetVT == MVT::f32) || in X86FastEmitSSESelect()
2790 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
2971 if (!Subtarget->hasSSE1()) in fastLowerIntrinsicCall()
3137 if (!Subtarget->hasSSE1()) in fastLowerArguments()
3497 assert((Subtarget->hasSSE1() || !NumXMMRegs) in fastLowerCall()
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H A DX86ISelLoweringCall.cpp273 if (Subtarget.hasSSE1()) in getByValTypeAlignment()
306 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) && in getOptimalMemOpType()
330 return Subtarget.hasSSE1(); in isSafeMemOpType()
789 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerReturn()
1121 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerCallResult()
1442 if (isSoftFloat || !Subtarget.hasSSE1()) in get64BitArgumentXMMs()
1524 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) && in createVarArgAreaAndStoreRegisters()
2286 (Subtarget.hasSSE1() || !M->getModuleFlag("SkipRaxSetup"))) { in LowerCall()
2301 assert((Subtarget.hasSSE1() || !NumXMMRegs) in LowerCall()
H A DX86RegisterInfo.cpp287 bool HasSSE = Subtarget.hasSSE1(); in getCalleeSavedRegs()
424 bool HasSSE = Subtarget.hasSSE1(); in getCallPreservedMask()
699 if (ST.hasSSE1() && in isArgumentRegister()
H A DX86LegalizerInfo.cpp
H A DX86TargetTransformInfo.cpp166 if (Vector && !ST->hasSSE1()) in getNumberOfRegisters()
213 if (ST->hasSSE1() && PreferVectorWidth >= 128) in getRegisterBitWidth()
1441 if (ST->hasSSE1()) in getArithmeticInstrCost()
2163 if (ST->hasSSE1()) in getShuffleCost()
3445 if (ST->hasSSE1()) in getCmpSelInstrCost()
4425 if (ST->hasSSE1()) in getIntrinsicInstrCost()
5969 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); in isLegalNTLoad()
5994 return ST->hasSSE1(); in isLegalNTStore()
H A DX86ISelLowering.cpp719 } else if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1() && in X86TargetLowering()
875 if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) { in X86TargetLowering()
1043 if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) { in X86TargetLowering()
3256 (VT == MVT::f32 && Subtarget.hasSSE1()) || VT == MVT::f16; in isScalarFPTypeInSSEReg()
3328 if (!Subtarget.hasSSE1() || VT.getSizeInBits() < 128) in hasAndNot()
22842 if ((VT == MVT::f32 && Subtarget.hasSSE1()) || in getSqrtEstimate()
22843 (VT == MVT::v4f32 && Subtarget.hasSSE1() && Reciprocal) || in getSqrtEstimate()
22893 if ((VT == MVT::f32 && Subtarget.hasSSE1()) || in getRecipEstimate()
22894 (VT == MVT::v4f32 && Subtarget.hasSSE1()) || in getRecipEstimate()
24741 assert(Subtarget.hasSSE1() && "Expected SSE"); in LowerStore()
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H A DX86InstrInfo.cpp10640 if (!ST.hasSSE1()) in buildClearRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp171 bool HasSSE1 = ST->hasSSE1(); in getPartialMappingIdx()
H A DX86LegalizerInfo.cpp36 bool HasSSE1 = Subtarget.hasSSE1(); in X86LegalizerInfo()