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Searched refs:getVT (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp230 MVT MVT::getVT(Type *Ty, bool HandleUnknown){ in getVT() function in MVT
263 getVT(VTy->getElementType(), /*HandleUnknown=*/ false), in getVT()
277 return MVT::getVT(Ty, HandleUnknown); in getEVT()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DDAGISelMatcher.h693 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
842 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
865 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
891 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
1033 MVT::SimpleValueType getVT(unsigned i) const { in getVT() function
H A DDAGISelMatcher.cpp412 return CVT->getVT() != getVT(); in isContradictoryImpl()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherEmitter.cpp701 << getEnumName(cast<CheckValueTypeMatcher>(N)->getVT()) << ",\n"; in EmitMatcher()
758 MVT::SimpleValueType VT = cast<EmitIntegerMatcher>(N)->getVT(); in EmitMatcher()
779 MVT::SimpleValueType VT = cast<EmitStringIntegerMatcher>(N)->getVT(); in EmitMatcher()
799 MVT::SimpleValueType VT = Matcher->getVT(); in EmitMatcher()
962 OS << getEnumName(EN->getVT(i)) << ", "; in EmitMatcher()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h477 static MVT getVT(Type *Ty, bool HandleUnknown = false);
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp292 cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) { in selectSExti32()
H A DLoongArchISelLowering.cpp1599 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLT(MVT::i32)) in lowerUINT_TO_FP()
1624 dyn_cast<VTSDNode>(Op0.getOperand(1))->getVT().bitsLE(MVT::i32)) in lowerSINT_TO_FP()
3465 if ((TypeNode->getVT() == MVT::i8) || (TypeNode->getVT() == MVT::i16)) { in checkValueWidth()
3473 if ((TypeNode->getVT() == MVT::i8) || (TypeNode->getVT() == MVT::i16)) { in checkValueWidth()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp633 N0.hasOneUse() && cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i32) { in tryShrinkShlLogicImm()
732 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits(); in trySignedBitfieldExtract()
1195 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits(); in Select()
1287 cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32) { in Select()
1314 cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32; in Select()
2884 cast<VTSDNode>(N.getOperand(1))->getVT().getSizeInBits() == Bits) { in selectSExtBits()
H A DRISCVInstrInfo.td1207 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
1213 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp558 MVT VT = MVT::getVT(Shuffles[0]->getType()); in deinterleave8bitStride3()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1614 : cast<VTSDNode>(N.getOperand(1))->getVT(); in DetectUseSxtw()
1683 if (T->getVT().getSizeInBits() == NumBits) { in keepsLowBits()
1756 return VN->getVT().getSizeInBits() <= 16; in isPositiveHalfWord()
H A DHexagonISelLowering.cpp1079 EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerSETCC()
2114 Info.memVT = MVT::getVT(ElTy); in getTgtMemIntrinsic()
2139 Info.memVT = MVT::getVT(VecTy); in getTgtMemIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1199 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps()
3680 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3856 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
4151 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
4476 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
4479 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
4591 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits(); in ComputeNumSignBits()
4598 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getScalarSizeInBits(); in ComputeNumSignBits()
7097 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
7109 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
[all …]
H A DSelectionDAGDumper.cpp764 OS << ":" << N->getVT(); in print_details()
H A DSelectionDAGISel.cpp2905 if (cast<VTSDNode>(N)->getVT() == VT) in CheckValueType()
2909 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL); in CheckValueType()
H A DDAGCombiner.cpp3201 if (TN->getVT() == MVT::i1) { in visitADDLikeCommutative()
4048 if (TN->getVT() == MVT::i1) { in visitSUB()
6589 cast<VTSDNode>(Op.getOperand(1))->getVT() : in SearchForAndLoads()
10961 VT0 = cast<VTSDNode>(Op0.getOperand(1))->getVT(); in foldABSToABD()
10962 VT1 = cast<VTSDNode>(Op1.getOperand(1))->getVT(); in foldABSToABD()
11012 EVT ExtVT = cast<VTSDNode>(N0.getOperand(1))->getVT(); in visitABS()
13596 EVT ExtVT = cast<VTSDNode>(N0->getOperand(1))->getVT(); in visitSIGN_EXTEND()
14339 EVT AssertVT = cast<VTSDNode>(N1)->getVT(); in visitAssertExt()
14343 AssertVT == cast<VTSDNode>(N0.getOperand(1))->getVT()) in visitAssertExt()
14355 EVT BigA_AssertVT = cast<VTSDNode>(BigA.getOperand(1))->getVT(); in visitAssertExt()
[all …]
H A DTargetLowering.cpp835 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyMultipleUseDemandedBits()
2350 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
2628 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
4772 !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(), in SimplifySetCC()
4774 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); in SimplifySetCC()
4881 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) in SimplifySetCC()
11138 EVT SatVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); in expandFP_TO_INT_SAT()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp224 unsigned Width = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in LowerSIGN_EXTEND_INREG()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp888 MVT VT = MVT::getVT(ReadReg->getType()); in isReadRegisterSourceOfDivergence()
H A DSIISelLowering.cpp1268 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType()); in getTgtMemIntrinsic()
1297 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1311 Info.memVT = MVT::getVT(CI.getOperand(0)->getType()); in getTgtMemIntrinsic()
1320 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1333 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1343 Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT? in getTgtMemIntrinsic()
1366 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1378 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
11756 NarrowVT = VTSign->getVT(); in calculateSrcByte()
11951 NarrowBitWidth = VTSign->getVT().getSizeInBits(); in calculateByteProvider()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4494 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerVectorFP_TO_INT_SAT()
4576 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
6978 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerOperation()
9791 cast<VTSDNode>(Val.getOperand(1))->getVT().getFixedSizeInBits() - in lookThroughSignExtension()
15556 MVT EleVT = MVT::getVT(VecTy).getVectorElementType(); in getTgtMemIntrinsic()
15594 MVT EleVT = MVT::getVT(VecTy).getVectorElementType(); in getTgtMemIntrinsic()
15615 Info.memVT = MVT::getVT(ValTy); in getTgtMemIntrinsic()
15626 Info.memVT = MVT::getVT(ValTy); in getTgtMemIntrinsic()
15654 Info.memVT = MVT::getVT(I.getType()); in getTgtMemIntrinsic()
15665 Info.memVT = MVT::getVT(I.getOperand(0)->getType()); in getTgtMemIntrinsic()
[all …]
H A DAArch64ISelDAGToDAG.cpp810 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
2555 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits(); in isBitfieldExtractOpFromSExtInReg()
7155 return cast<VTSDNode>(Root->getOperand(3))->getVT(); in getMemVTFromNode()
7157 return cast<VTSDNode>(Root->getOperand(4))->getVT(); in getMemVTFromNode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp1099 MVT VT = MVT::getVT(Outs[I].Ty); in checkReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1921 cast<VTSDNode>(Op.getOperand(1).getNode())->getVT().getSimpleVT(); in LowerSIGN_EXTEND_INREG()
2461 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1066 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
1067 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;

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