/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMIPeephole.cpp | 111 MachineInstr *DefInsn = MRI->getVRegDef(Reg); in isCopyFrom32Def() 126 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg()); in isPhiFrom32Def() 163 MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg()); in isMovFrom32Def() 198 MachineInstr *SllMI = MRI->getVRegDef(ShfReg); in eliminateZExtSeq() 212 MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg()); in eliminateZExtSeq()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CombinerHelperVectorOps.cpp | 407 GAdd *Add = cast<GAdd>(MRI.getVRegDef(MO.getReg())); in matchAddOfVScale() 408 GVScale *LHSVScale = cast<GVScale>(MRI.getVRegDef(Add->getLHSReg())); in matchAddOfVScale() 409 GVScale *RHSVScale = cast<GVScale>(MRI.getVRegDef(Add->getRHSReg())); in matchAddOfVScale() 426 GMul *Mul = cast<GMul>(MRI.getVRegDef(MO.getReg())); in matchMulOfVScale() 427 GVScale *LHSVScale = cast<GVScale>(MRI.getVRegDef(Mul->getLHSReg())); in matchMulOfVScale() 447 GSub *Sub = cast<GSub>(MRI.getVRegDef(MO.getReg())); in matchSubOfVScale() 448 GVScale *RHSVScale = cast<GVScale>(MRI.getVRegDef(Sub->getRHSReg())); in matchSubOfVScale() 467 GShl *Shl = cast<GShl>(MRI.getVRegDef(MO.getReg())); in matchShlOfVScale() 468 GVScale *LHSVScale = cast<GVScale>(MRI.getVRegDef(Shl->getSrcReg())); in matchShlOfVScale()
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H A D | GIMatchTableExecutor.cpp | 50 MachineInstr *RootI = MRI.getVRegDef(Root.getReg()); in isBaseWithConstantOffset() 55 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg()); in isObviouslySafeToFold()
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H A D | CombinerHelper.cpp | 308 MachineInstr *Def = MRI.getVRegDef(Reg); in matchCombineConcatVectors() 380 dyn_cast<GConcatVectors>(MRI.getVRegDef(MI.getOperand(1).getReg())); in matchCombineShuffleConcat() 382 dyn_cast<GConcatVectors>(MRI.getVRegDef(MI.getOperand(2).getReg())); in matchCombineShuffleConcat() 915 GAnyLoad *LoadMI = dyn_cast<GAnyLoad>(MRI.getVRegDef(SrcReg)); in matchCombineLoadWithAndMask() 1087 GLoad *LoadDef = cast<GLoad>(MRI.getVRegDef(LoadReg)); in applySextInRegOfLoad() 1189 auto *PtrDef = MRI.getVRegDef(Ptr); in findPostIndexCandidate() 1214 MachineInstr *OffsetDef = MRI.getVRegDef(Offset); in findPostIndexCandidate() 1452 auto *OldCst = MRI.getVRegDef(MatchInfo.Offset); in applyCombineIndexedLoadStore() 1718 MachineInstr *Add2Def = MRI.getVRegDef(Add2); in matchPtrAddImmedChain() 1996 auto *SrcDef = MRI.getVRegDef(SrcReg); in matchCommuteShift() [all …]
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H A D | Utils.cpp | 98 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass() 335 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) && in getConstantVRegValWithLookThrough() 453 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantFPVRegVal() 462 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies() 472 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies() 805 const MachineInstr *DefMI = MRI.getVRegDef(Val); in isKnownNeverNaN() 912 MachineInstr *Def = MRI.getVRegDef(LiveIn); in getFunctionLiveInPhysReg() 1358 if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element))) in getAnyConstantSplat() 1507 const MachineInstr *ElementDef = MRI.getVRegDef(MI.getOperand(I).getReg()); in isConstantOrConstantVector() 1642 DeadInstChain.insert(MRI.getVRegDef(Op.getReg())); in saveUsesAndErase() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 442 MachineInstr *DI = MRI->getVRegDef(PhiOpReg); in findInductionRegister() 450 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) { in findInductionRegister() 469 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister() 505 IVOp = MRI->getVRegDef(F->first); in findInductionRegister() 608 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); in getLoopTripCount() 655 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount() 703 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount() 709 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount() 713 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount() 719 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount() [all …]
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H A D | HexagonVExtract.cpp | 78 MachineInstr *DI = MRI.getVRegDef(ExtIdxR); in genElemLoad() 149 MachineInstr *DefI = MRI.getVRegDef(VecR); in runOnMachineFunction() 183 MachineInstr *AlignaI = MRI.getVRegDef(AR); in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 146 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() 157 DefMI = MRI->getVRegDef(SrcReg); in hasLoopHazard() 165 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() 171 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
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H A D | A15SDOptimizer.cpp | 157 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane() 250 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern() 251 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern() 302 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern() 345 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopies() 372 MachineInstr *NewMI = MRI->getVRegDef(Reg); in elideCopiesAndPHIs() 380 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopiesAndPHIs() 602 MachineInstr *Def = MRI->getVRegDef(I); in runOnInstruction()
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H A D | MVETPAndVPTOptimisationsPass.cpp | 104 MI = MRI->getVRegDef(MI->getOperand(1).getReg()); in INITIALIZE_PASS_DEPENDENCY() 153 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI); in findLoopComponents() 162 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI); in findLoopComponents() 175 LoopStart = LookThroughCOPY(MRI->getVRegDef(StartReg), MRI); in findLoopComponents() 493 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop() 939 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs() 950 MachineInstr *Def = MRI->getVRegDef(GPR); in ReplaceConstByVPNOTs() 969 DeadInstructions.insert(MRI->getVRegDef(GPR)); in ReplaceConstByVPNOTs() 987 DeadInstructions.insert(MRI->getVRegDef(GPR)); in ReplaceConstByVPNOTs()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCMIPeephole.cpp | 224 return MRI->getVRegDef(Reg); in getVRegDefOrNull() 232 MachineInstr *MI = MRI->getVRegDef(Reg); in getKnownLeadingZeroCount() 366 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs() 408 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs() 581 MachineInstr *RootPHI = MRI->getVRegDef(Src); in simplifyCode() 651 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); in simplifyCode() 668 MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1); in simplifyCode() 810 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() 820 MachineInstr *Splt = MRI->getVRegDef(ConvReg); in simplifyCode() 877 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64PostLegalizerCombiner.cpp | 92 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd() 95 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd() 100 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) { in matchExtractVecEltPairwiseAdd() 127 unsigned Opc = MRI.getVRegDef(R)->getOpcode(); in isSignExtended() 133 return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_ZEXT; in isZeroExtended() 321 *MRI.getVRegDef(Store.getValueReg()), MRI); in matchSplitStoreZero128() 405 *MRI.getVRegDef(MI.getOperand(2).getReg()), MRI); in matchCombineMulCMLT() 407 *MRI.getVRegDef(AndMI->getOperand(2).getReg()), MRI); in matchCombineMulCMLT() 409 *MRI.getVRegDef(LShrMI->getOperand(2).getReg()), MRI); in matchCombineMulCMLT() 731 GPtrAdd *PtrAdd = cast<GPtrAdd>(MRI.getVRegDef(PtrReg)); in optimizeConsecutiveMemOpAddressing()
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H A D | AArch64RegisterBankInfo.cpp | 551 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints() 786 auto ScalarDef = MRI.getVRegDef(ScalarReg); in getInstrMapping() 896 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 907 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 966 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 1052 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 1056 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() == in getInstrMapping()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVVectorPeephole.cpp | 87 MachineInstr *Def = MRI->getVRegDef(VL.getReg()); in convertToVLMAX() 97 Def = MRI->getVRegDef(Def->getOperand(1).getReg()); in convertToVLMAX() 101 Def = MRI->getVRegDef(Def->getOperand(1).getReg()); in convertToVLMAX() 137 MaskDef = MRI->getVRegDef(SrcReg); in isAllOnesMask()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizationArtifactCombiner.h | 80 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt() 98 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt() 161 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineZExt() 173 markDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineZExt() 178 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineZExt() 223 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineSExt() 237 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineSExt() 242 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineSExt() 271 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineTrunc() 352 markInstAndDefDead(MI, *MRI.getVRegDef(TruncSrc), DeadInsts); in tryCombineTrunc() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
H A D | SPIRVPreLegalizer.cpp | 69 auto *BuildVec = MRI.getVRegDef(SrcReg); in addConstantsToTrack() 87 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in addConstantsToTrack() 105 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack() 139 MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg()); in foldConstantsIntoIntrinsics() 255 MRI.getVRegDef(MI->getOperand(1).getReg())) { in propagateSPIRVType() 279 MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr; in propagateSPIRVType() 374 MachineInstr *Def = MRI.getVRegDef(Reg); in insertAssignInstr() 460 MachineInstr *Def = MRI.getVRegDef(Reg); in generateAssignInstrs() 471 MachineInstr *Def = MRI.getVRegDef(Reg); in generateAssignInstrs() 519 MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg()); in generateAssignInstrs() [all …]
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H A D | SPIRVUtils.cpp | 256 MachineInstr *MI = MRI->getVRegDef(ConstReg); in getDefInstrMaybeConstant() 259 ? MRI->getVRegDef(MI->getOperand(1).getReg()) in getDefInstrMaybeConstant() 264 return MRI->getVRegDef(ConstReg); in getDefInstrMaybeConstant() 268 return MRI->getVRegDef(ConstReg); in getDefInstrMaybeConstant() 270 return MRI->getVRegDef(ConstReg); in getDefInstrMaybeConstant()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineCycleAnalysis.cpp | 141 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!"); in isCycleInvariant() 145 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent())) in isCycleInvariant()
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H A D | ModuloSchedule.cpp | 404 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal)); in generateExistingPhis() 455 MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1); in generateExistingPhis() 463 InstOp1 = MRI.getVRegDef(PhiOp1); in generateExistingPhis() 477 if (MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1)) in generateExistingPhis() 481 MachineInstr *PhiInst = MRI.getVRegDef(LoopVal); in generateExistingPhis() 650 if (MachineInstr *InstOp2 = MRI.getVRegDef(PhiOp2)) in generatePhis() 816 MachineInstr *MI = MRI.getVRegDef(LCDef); in splitLifetimes() 946 MachineInstr *BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() 949 BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() 1048 MachineInstr *Def = MRI.getVRegDef(reg); in updateInstruction() [all …]
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H A D | OptimizePHIs.cpp | 115 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle() 122 SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
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H A D | MIRVRegNamerUtils.cpp | 81 return MRI.getVRegDef(MO.getReg())->getOpcode(); in getInstructionOpcodeHash() 143 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
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H A D | LiveVariables.cpp | 159 assert(MRI->getVRegDef(Reg) && "Register use before def!"); in HandleVirtRegUse() 194 if (MBB == MRI->getVRegDef(Reg)->getParent()) in HandleVirtRegUse() 205 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred); in HandleVirtRegUse() 604 MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(), in runOnBlock() 665 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) in analyze() 817 const MachineInstr *Def = MRI.getVRegDef(Reg); in isLiveIn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastPreTileConfig.cpp | 292 MachineInstr *MI = MRI->getVRegDef(TileReg); in getShape() 350 MachineInstr *TileDefMI = MRI->getVRegDef(InTileReg); in convertPHI() 376 MachineInstr *TileLoad = MRI->getVRegDef(InTileReg); in convertPHI() 463 DefMI = MRI->getVRegDef(InTileReg); in canonicalizePHIs() 604 MachineInstr *RowMI = MRI->getVRegDef(RowMO->getReg()); in configBasicBlock() 605 MachineInstr *ColMI = MRI->getVRegDef(ColMO->getReg()); in configBasicBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFixBrTableDefaults.cpp | 62 auto ExtMI = MF.getRegInfo().getVRegDef(MI.getOperand(0).getReg()); in fixBrTableIndex() 128 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg()); in fixBrTableDefault()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFoldOperands.cpp | 660 MachineInstr *Def = MRI->getVRegDef(UseReg); in getRegSeqInit() 668 for (MachineInstr *SubDef = MRI->getVRegDef(Sub->getReg()); in getRegSeqInit() 671 SubDef = MRI->getVRegDef(Sub->getReg())) { in getRegSeqInit() 717 MachineInstr *Def = MRI->getVRegDef(UseReg); in tryToFoldACImm() 1196 MachineInstr *Def = MRI->getVRegDef(Op.getReg()); in getImmOrMaterializedImm() 1359 MachineInstr *SrcDef = MRI->getVRegDef(Src1); in tryFoldZeroHighBits() 1498 InstToErase = MRI->getVRegDef(SrcReg); in tryFoldFoldableCopy() 1567 MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg()); in tryFoldClamp() 1744 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg()); in tryFoldOMod() 1792 const MachineInstr *SubDef = MRI->getVRegDef(Op->getReg()); in tryFoldRegSequence() [all …]
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