Searched refs:getStage (Results 1 – 11 of 11) sorted by relevance
31 OS << "[stage " << getStage(MI) << " @" << getCycle(MI) << "c] " << *MI; in print()80 int DefStage = Schedule.getStage(MI); in expand()87 int UseStage = Schedule.getStage(UseMI); in expand()140 unsigned StageNum = Schedule.getStage(CI); in generatePipelinedLoop()222 if (Schedule.getStage(&*BBI) == StageNum) { in generateProlog()300 if ((unsigned)Schedule.getStage(In) == StageNum) { in generateEpilog()403 int StageScheduled = Schedule.getStage(&*BBI); in generateExistingPhis()404 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal)); in generateExistingPhis()458 int PhiStage = Schedule.getStage(InstOp1); in generateExistingPhis()464 int PhiOpStage = Schedule.getStage(InstOp1); in generateExistingPhis()[all …]
84 LiveRangeStage getStage(Register Reg) const { return Info[Reg].Stage; } in getStage() function86 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage() function87 return getStage(VirtReg.reg()); in getStage()103 return getStage(Reg); in getOrInitStage()
152 bool CanSplit = RA.getExtraInfo().getStage(B) < RS_Spill; in shouldEvict()224 if (RA.getExtraInfo().getStage(*Intf) == RS_Done) in canEvictInterferenceBasedOnCost()
307 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); in getPriority()1242 if (ExtraInfo->getStage(VirtReg) >= RS_Split2) in trySplitAroundHintReg()1645 bool ProgressRequired = ExtraInfo->getStage(VirtReg) >= RS_Split2; in tryLocalSplit()1802 if (ExtraInfo->getStage(VirtReg) >= RS_Spill) in trySplit()1824 if (ExtraInfo->getStage(VirtReg) < RS_Split2) { in trySplit()1895 if (((ExtraInfo->getStage(*Intf) == RS_Done && in mayRecolorAllInterferences()1968 assert((ExtraInfo->getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) && in tryLastChanceRecoloring()2177 if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) { in tryAssignCSRFirstTime()2189 if (ExtraInfo->getStage(VirtReg) < RS_Split) { in tryAssignCSRFirstTime()2437 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg); in selectOrSplitImpl()[all …]
639 if (RA.getExtraInfo().getStage(*Intf) == RS_Done) in loadInterferenceFeatures()873 MaxStage, static_cast<int64_t>(RA.getExtraInfo().getStage(LI))); in extractFeatures()875 MinStage, static_cast<int64_t>(RA.getExtraInfo().getStage(LI))); in extractFeatures()
299 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); in getPriorityImpl()
540 CU->getStage() == CompileUnit::Stage::LivenessAnalysisDone) in link()598 if (CU.getStage() >= DoUntilStage) in linkSingleCompileUnit()601 switch (CU.getStage()) { in linkSingleCompileUnit()1058 if (ModuleUnit.Unit->getStage() != CompileUnit::Stage::Skipped) in forEachObjectSectionsSet()1068 if (CU->getStage() != CompileUnit::Stage::Skipped) in forEachObjectSectionsSet()1081 if (ModuleUnit.Unit->getStage() != CompileUnit::Stage::Skipped) in forEachCompileAndTypeUnit()1087 if (CU->getStage() != CompileUnit::Stage::Skipped) in forEachCompileAndTypeUnit()1096 if (ModuleUnit.Unit->getStage() != CompileUnit::Stage::Skipped) in forEachCompileUnit()1102 if (CU->getStage() != CompileUnit::Stage::Skipped) in forEachCompileUnit()
77 if (getStage() < Stage::Loaded) in maybeResetToLoadedStage()94 if (getStage() < Stage::Cloned) { in maybeResetToLoadedStage()404 enum Stage ReferredCUStage = RefCU->getStage(); in resolveDIEReference()
135 int getStage(MachineInstr *MI) { in getStage() function361 unsigned getStage(MachineInstr *MI) { in getStage() function364 return Schedule.getStage(MI); in getStage()