| /freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/ |
| H A D | RegisterFileStatistics.cpp | 22 const MCSchedModel &SM = STI.getSchedModel(); in RegisterFileStatistics()
121 assert(STI.getSchedModel().hasExtraProcessorInfo() && in printView()
124 STI.getSchedModel().getExtraProcessorInfo(); in printView()
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| H A D | ResourcePressureView.cpp | 27 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in ResourcePressureView()
128 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printResourcePressurePerIter()
179 printColumnNames(FOS, getSubTargetInfo().getSchedModel()); in printResourcePressurePerInst()
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| H A D | SchedulerStatistics.cpp | 22 : SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0), in SchedulerStatistics()
25 Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) { in SchedulerStatistics()
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| H A D | InstructionInfoView.cpp | 61 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printView()
191 const MCSchedModel &SM = STI.getSchedModel(); in collectData()
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| H A D | TimelineView.cpp | 46 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in onReservedBuffers()
171 getSubTargetInfo().getSchedModel().MicroOpBufferSize); in printWaitTimeEntry()
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| H A D | BottleneckAnalysis.cpp | 445 : InstructionView(sti, Printer, S), Tracker(sti.getSchedModel()), in BottleneckAnalysis()
612 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printBottleneckHints()
666 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in toJSON()
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 38 const MCSchedModel &SM = STI.getSchedModel(); in InstrBuilder()
40 computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks); in InstrBuilder()
47 const MCSchedModel &SM = STI.getSchedModel(); in initializeUsedResources()
271 const MCSchedModel &SM = STI.getSchedModel(); in populateWrites()
545 const MCSchedModel &SM = STI.getSchedModel(); in getVariantSchedClassID()
562 assert(STI.getSchedModel().hasInstrSchedModel() && in createInstrDescImpl()
568 const MCSchedModel &SM = STI.getSchedModel(); in createInstrDescImpl()
704 *STI.getSchedModel().getSchedClassDesc(D.SchedClassID); in createInstruction()
719 unsigned ProcID = STI.getSchedModel().getProcessorID(); in createInstruction()
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| H A D | Context.cpp | 34 const MCSchedModel &SM = STI.getSchedModel(); in createDefaultPipeline()
75 const MCSchedModel &SM = STI.getSchedModel(); in createInOrderPipeline()
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| /freebsd/contrib/llvm-project/llvm/tools/llvm-mca/ |
| H A D | PipelinePrinter.cpp | 52 const MCSchedModel &SM = STI.getSchedModel(); in getJSONSimulationParameters()
82 const MCSchedModel &SM = STI.getSchedModel(); in getJSONTargetInfo()
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| H A D | llvm-mca.cpp | 427 if (!STI->getSchedModel().hasInstrSchedModel()) { in main()
433 if (STI->getSchedModel().InstrItineraries) in main()
441 bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder(); in main()
575 const MCSchedModel &SM = STI->getSchedModel(); in main()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSubtarget.cpp | 155 ? getSchedModel().LoadLatency + 1 in getMaxBuildIntsCost()
205 return getSchedModel().hasInstrSchedModel(); in enableMachinePipeliner()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetSubtargetInfo.cpp | 50 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
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| H A D | VLIWMachineScheduler.cpp | 272 SchedModel = DAG->getSchedModel(); in initialize()
279 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); in initialize()
289 Top.ResourceModel = createVLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
290 Bot.ResourceModel = createVLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
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| H A D | TargetSchedule.cpp | 47 SchedModel = TSInfo->getSchedModel(); in init()
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/ |
| H A D | InOrderIssueStage.cpp | 49 : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU), in InOrderIssueStage()
53 return STI.getSchedModel().IssueWidth; in getIssueWidth()
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| H A D | DispatchStage.cpp | 34 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
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| /freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 515 const MCSchedModel &SM = STI.getSchedModel(); in collectWrites()
582 const MCSchedModel &SM = STI.getSchedModel(); in checkRAWHazards()
646 const MCSchedModel &SM = STI.getSchedModel(); in addRegisterRead()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 321 : TII(TII), SchedModel(TII.getSchedModel()) { in BranchWeightCostModel()
395 if (!TII->getSchedModel().hasInstrSchedModel()) in removeExeczBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSchedule.cpp | 101 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.cpp | 155 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; in enableMachinePipeliner()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 166 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel() function
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 283 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.cpp | 362 return getSchedModel().hasInstrSchedModel() && useMachinePipeliner(); in enableMachinePipeliner()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 169 const MCSchedModel &SCModel = STI->getSchedModel(); in emitLatency()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 434 const InstrItinerary *II = STI.getSchedModel().InstrItineraries; in getCVIResources()
453 const InstrItinerary *II = STI.getSchedModel().InstrItineraries; in getUnits()
464 const InstrItinerary *II = STI.getSchedModel().InstrItineraries; in getOtherReservedSlots()
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