Home
last modified time | relevance | path

Searched refs:getSUnit (Results 1 – 25 of 33) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAG.cpp111 if (!Required && PredDep.getSUnit() == D.getSUnit()) in addPred()
117 SUnit *PredSU = PredDep.getSUnit(); in addPred()
130 D.getSUnit()->setHeightDirty(); in addPred()
138 SUnit *N = D.getSUnit(); in addPred()
183 SUnit *N = D.getSUnit(); in removePred()
225 SUnit *SuccSU = SuccDep.getSUnit(); in setDepthDirty()
240 SUnit *PredSU = PredDep.getSUnit(); in setHeightDirty()
273 SUnit *PredSU = PredDep.getSUnit(); in ComputeDepth()
304 SUnit *SuccSU = SuccDep.getSUnit(); in ComputeHeight()
330 unsigned MaxDepth = BestI->getSUnit()->getDepth(); in biasCriticalPath()
[all …]
H A DMacroFusion.cpp41 return SI.getSUnit(); in getPredClusterSU()
95 if (SI.getSUnit() == &SecondSU) in fuseInstructionPair()
99 if (SI.getSUnit() == &FirstSU) in fuseInstructionPair()
112 SUnit *SU = SI.getSUnit(); in fuseInstructionPair()
125 SUnit *SU = SI.getSUnit(); in fuseInstructionPair()
209 SUnit &DepSU = *Dep.getSUnit(); in scheduleAdjacentImpl()
H A DVLIWMachineScheduler.cpp97 if (S.getSUnit() == SUu && S.getLatency() > 0) in hasDependence()
309 unsigned PredReadyCycle = PI.getSUnit()->TopReadyCycle; in releaseTopNode()
327 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; in releaseBottomNode()
551 if (!Pred.getSUnit()->isScheduled && (Pred.getSUnit() != SU2)) in isSingleUnscheduledPred()
566 if (!Succ.getSUnit()->isScheduled && (Succ.getSUnit() != SU2)) in isSingleUnscheduledSucc()
664 if (isSingleUnscheduledPred(SI.getSUnit(), SU)) in SchedulingCost()
670 if (isSingleUnscheduledSucc(PI.getSUnit(), SU)) in SchedulingCost()
708 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()
710 Top.ResourceModel->isInPacket(PI.getSUnit())) { in SchedulingCost()
717 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
[all …]
H A DLatencyPriorityQueue.cpp59 SUnit &Pred = *P.getSUnit(); in getSingleUnscheduledPred()
77 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU) in push()
91 AdjustPriorityOfUnscheduledPreds(Succ.getSUnit()); in scheduledNode()
H A DWindowScheduler.cpp433 auto *SU = DAG.getSUnit(&MI); in calculateMaxCycle()
439 auto *PredMI = Pred.getSUnit()->getInstr(); in calculateMaxCycle()
497 auto *SU = TripleDAG->getSUnit(&MI); in calculateStallCycle()
500 if (Succ.isWeak() || Succ.getSUnit() == &TripleDAG->ExitSU) in calculateStallCycle()
508 auto *SuccMI = Succ.getSUnit()->getInstr(); in calculateStallCycle()
537 auto *SU = TripleDAG->getSUnit(&Phi); in schedulePhi()
544 auto *SuccMI = Succ.getSUnit()->getInstr(); in schedulePhi()
H A DScheduleDAGInstrs.cpp1243 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU)) in addEdge()
1245 Topo.AddPredQueued(SuccSU, PredDep.getSUnit()); in addEdge()
1321 unsigned PredNum = PredDep.getSUnit()->NodeNum; in visitPostorderNode()
1349 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount; in visitPostorderEdge()
1355 ConnectionPairs.emplace_back(PredDep.getSUnit(), Succ); in visitCrossEdge()
1402 const SUnit *PredSU = PredDep.getSUnit(); in joinPredSubtree()
1478 !SuccDep.getSUnit()->isBoundaryNode()) in hasDataSucc()
1505 || PredDep.getSUnit()->isBoundaryNode()) { in compute()
1509 if (Impl.isVisited(PredDep.getSUnit())) { in compute()
1513 Impl.visitPreorder(PredDep.getSUnit()); in compute()
[all …]
H A DMachineScheduler.cpp943 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
978 SUnit *PredSU = PredEdge->getSUnit(); in releasePred()
1249 const unsigned FirstCycle = getSUnit(&*(std::begin(*this)))->TopReadyCycle; in dumpScheduleTraceTopDown()
1250 unsigned LastCycle = getSUnit(&*(std::prev(std::end(*this))))->TopReadyCycle; in dumpScheduleTraceTopDown()
1252 SUnit *SU = getSUnit(&MI); in dumpScheduleTraceTopDown()
1270 SUnit *SU = getSUnit(&MI); in dumpScheduleTraceTopDown()
1331 const int FirstCycle = getSUnit(&*(std::begin(*this)))->BotReadyCycle; in dumpScheduleTraceBottomUp()
1332 int LastCycle = getSUnit(&*(std::prev(std::end(*this))))->BotReadyCycle; in dumpScheduleTraceBottomUp()
1334 SUnit *SU = getSUnit(&MI); in dumpScheduleTraceBottomUp()
1352 SUnit *SU = getSUnit(&MI); in dumpScheduleTraceBottomUp()
[all …]
H A DAggressiveAntiDepBreaker.cpp274 const SUnit *PredSU = Pred.getSUnit(); in CriticalPathStep()
287 return (Next) ? Next->getSUnit() : nullptr; in CriticalPathStep()
827 SUnit *NextSU = Edge->getSUnit(); in BreakAntiDependencies()
871 if (Pred.getSUnit() == NextSU ? (Pred.getKind() != SDep::Anti || in BreakAntiDependencies()
880 if ((Pred.getSUnit() == NextSU) && (Pred.getKind() != SDep::Anti) && in BreakAntiDependencies()
885 } else if ((Pred.getSUnit() != NextSU) && in BreakAntiDependencies()
H A DMachinePipeliner.cpp865 NewInstrChanges[KV.first] = InstrChanges[getSUnit(KV.first)]; in schedule()
938 SUnit *SuccSU = SI.getSUnit(); in isSuccOrder()
1210 SUnit *SU = getSUnit(UseMI); in updatePhiDependences()
1230 SUnit *SU = getSUnit(DefMI); in updatePhiDependences()
1252 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
1287 SUnit *DefSU = getSUnit(DefMI); in changeDependences()
1294 SUnit *LastSU = getSUnit(LastMI); in changeDependences()
1304 if (P.getSUnit() == DefSU) in changeDependences()
1307 Topo.RemovePred(&I, D.getSUnit()); in changeDependences()
1313 if (P.getSUnit() == &I && P.getKind() == SDep::Order) in changeDependences()
[all …]
H A DCriticalAntiDepBreaker.cpp145 const SUnit *PredSU = P.getSUnit(); in CriticalPathStep()
555 const SUnit *NextSU = Edge->getSUnit(); in BreakAntiDependencies()
578 if (P.getSUnit() == NextSU in BreakAntiDependencies()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNMinRegStrategy.cpp90 for (auto PDep : SDep.getSUnit()->Preds) { in getReadySuccessors()
91 auto *PSU = PDep.getSUnit(); in getReadySuccessors()
180 if (S.getSUnit()->isBoundaryNode() || isScheduled(S.getSUnit()) || in bumpPredsPriority()
183 for (const auto &P : S.getSUnit()->Preds) { in bumpPredsPriority()
184 auto *PSU = P.getSUnit(); in bumpPredsPriority()
196 if (!P.getSUnit()->isBoundaryNode() && !isScheduled(P.getSUnit()) && in bumpPredsPriority()
197 Set.insert(P.getSUnit()).second) in bumpPredsPriority()
198 Worklist.push_back(P.getSUnit()); in bumpPredsPriority()
215 auto *SuccSU = S.getSUnit(); in releaseSuccessors()
H A DAMDGPUExportClustering.cpp69 SUnit *PredSU = Pred.getSUnit(); in buildCluster()
85 SUnit *PredSU = Pred.getSUnit(); in removeExportDependencies()
94 SUnit *ExportPredSU = ExportPred.getSUnit(); in removeExportDependencies()
129 removeExportDependencies(DAG, *Succ.getSUnit()); in apply()
H A DAMDGPUIGroupLP.cpp500 Succ->Preds, [&Pred](SDep &P) { return P.getSUnit() == Pred; }); in removeEdges()
1007 if (TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr())) { in apply()
1008 TempSU = Succ.getSUnit(); in apply()
1056 llvm::count_if(Succ.getSUnit()->Succs, [](const SDep &SuccSucc) { in apply()
1096 llvm::count_if(Succ.getSUnit()->Succs, [](const SDep &SuccSucc) { in apply()
1174 if (Succ.getSUnit() == SU && Succ.getKind() == SDep::Data) in apply()
1258 if (TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr())) { in apply()
1259 TempSU = Succ.getSUnit(); in apply()
1361 if (Succ.getSUnit()->Succs.size() >= 7) in analyzeDAG()
1406 return isCvt(Succ.getSUnit()->getInstr()->getOpcode()); in analyzeDAG()
[all …]
H A DSIMachineScheduler.cpp419 if (BC->isSUInBlock(Succ.getSUnit(), ID)) in undoSchedule()
429 SUnit *SuccSU = SuccEdge->getSUnit(); in undoReleaseSucc()
439 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
460 SUnit *SuccSU = Succ.getSUnit(); in releaseSuccessors()
493 NodeNum2Index.find(Succ.getSUnit()->NodeNum); in nodeScheduled()
640 if (PredDep.getSUnit() == &FromSU && in hasDataDependencyPred()
792 SUnit *Pred = PredDep.getSUnit(); in colorComputeReservedDependencies()
830 SUnit *Succ = SuccDep.getSUnit(); in colorComputeReservedDependencies()
907 SUnit *Succ = SuccDep.getSUnit(); in colorEndsAccordingToDependencies()
977 SUnit *Succ = SuccDep.getSUnit(); in colorMergeConstantLoadsNextGroup()
[all …]
H A DGCNILPSched.cpp66 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
110 unsigned Height = Succ.getSUnit()->getHeight(); in closestSucc()
275 auto *PredSU = PredEdge.getSUnit(); in releasePredecessors()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHazardRecognizer.cpp150 S.getSUnit()->NumPredsLeft == 1) { in EmitInstruction()
151 UsesDotCur = S.getSUnit(); in EmitInstruction()
165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
166 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
167 PrefVectorStoreNew = S.getSUnit(); in EmitInstruction()
H A DHexagonSubtarget.cpp272 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
279 for (SDep &PI : SI.getSUnit()->Preds) { in apply()
280 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order) in apply()
283 SI.getSUnit()->setDepthDirty(); in apply()
470 MachineInstr *DDst = DDep.getSUnit()->getInstr(); in adjustSchedDependency()
558 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()
607 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()
624 !I.getSUnit()->getInstr()->isPseudo()) in getZeroLatency()
625 return I.getSUnit(); in getZeroLatency()
702 if (ExclSrc.count(I.getSUnit()) == 0 && in isBestZeroLatency()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp225 Topo.AddPredQueued(SU, D.getSUnit()); in AddPredQueued()
233 Topo.AddPred(SU, D.getSUnit()); in AddPred()
241 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
401 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
566 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && in ReleasePredecessors()
568 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); in ReleasePredecessors()
823 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
845 assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() && in UnscheduleNodeBottomUp()
901 LiveRegGens[Reg] = Succ.getSUnit(); in UnscheduleNodeBottomUp()
904 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight()) in UnscheduleNodeBottomUp()
[all …]
H A DScheduleDAGFast.cpp130 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
161 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); in ReleasePredecessors()
184 if (LiveRegCycles[Succ.getReg()] == Succ.getSUnit()->getHeight()) { in ScheduleNodeBottomUp()
275 else if (Pred.getSUnit()->getNode() && in CopyAndMoveSuccessors()
276 Pred.getSUnit()->getNode()->isOperandOf(LoadNode)) in CopyAndMoveSuccessors()
288 if (ChainPred.getSUnit()) { in CopyAndMoveSuccessors()
304 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
311 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
348 SUnit *SuccSU = Succ.getSUnit(); in CopyAndMoveSuccessors()
384 SUnit *SuccSU = Succ.getSUnit(); in InsertCopiesAndMoveSuccs()
[all …]
H A DResourcePriorityQueue.cpp73 SUnit *PredSU = Pred.getSUnit(); in numberRCValPredInSU()
111 SUnit *SuccSU = Succ.getSUnit(); in numberRCValSuccInSU()
212 SUnit &PredSU = *Pred.getSUnit(); in getSingleUnscheduledPred()
229 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU) in push()
273 if (Succ.getSUnit() == SU) in isResourceAvailable()
498 if (Pred.isCtrl() || (Pred.getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
500 --Pred.getSUnit()->NumRegDefsLeft; in scheduledNode()
513 adjustPriorityOfUnscheduledPreds(Succ.getSUnit()); in scheduledNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
47 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isLoadAfterStore()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
73 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isBCTRAfterSet()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h152 SUnit *getSUnit() const;
455 if (Pred.getSUnit() == N) in isPred()
463 if (Succ.getSUnit() == N) in isSucc()
502 inline SUnit *SDep::getSUnit() const { return Dep.getPointer(); } in getSUnit() function
666 return Node->Preds[Operand].getSUnit();
H A DScheduleDAGInstrs.h312 SUnit *getSUnit(MachineInstr *MI) const;
424 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const { in getSUnit() function
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp495 for (SDep &PDep : SrcDep.getSUnit()->Preds) { in setBidirLatencies()
498 SrcDep.getSUnit()->setDepthDirty(); in setBidirLatencies()
531 SUnit &DepSU = *Dep.getSUnit(); in makeBundleAssumptions()
558 auto &DstInst = *Dep.getSUnit()->getInstr(); in memoryRAWHazard()
627 SUnit &DepSU = *Dep.getSUnit(); in modifyBypasses()
877 SUnit &DepSU = *Dep.getSUnit(); in modifyBypasses()
940 SUnit &DepSU = *Dep.getSUnit(); in modifyBypasses()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorMaskDAGMutation.cpp55 SUnit &DepSU = *Dep.getSUnit(); in isSoleUseCopyToV0()

12