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Searched refs:getSExtValue (Results 1 – 25 of 281) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td18 defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
21 defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
24 defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>;
27 defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
30 defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
33 defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
36 defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
39 defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
42 defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
45 defm s31_1ImmPred : ImmOpPred<[{ return isShiftedInt<32, 1>(N->getSExtValue());}]>;
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H A DHexagonOperands.td13 def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>;
19 int64_t v = (int64_t)N->getSExtValue();
23 int64_t v = (int64_t)N->getSExtValue();
H A DHexagonOptimizeSZextends.cpp102 if (!(C && C->getSExtValue() == 16)) in runOnFunction()
113 if (!(C && C->getSExtValue() == 16)) in runOnFunction()
H A DHexagonIntrinsics.td112 int64_t V = N->getSExtValue();
150 int32_t V = N->getSExtValue();
155 int32_t V = N->getSExtValue();
245 int64_t v = (int64_t)(64 - N->getSExtValue());
250 int64_t v = (int64_t)(128 - N->getSExtValue());
255 int32_t Imm = N->getSExtValue();
260 int32_t Imm = N->getSExtValue();
H A DHexagonISelDAGToDAG.cpp80 int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue(); in INITIALIZE_PASS()
217 CurDAG->getSignedTargetConstant(Inc->getSExtValue(), dl, MVT::i32); in LoadInstrForLoadIntrinsic()
402 SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), DL, MVT::i32); in SelectNewCircIntrinsic()
437 SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), DL, MVT::i32); in SelectNewCircIntrinsic()
480 int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue(); in SelectIndexedStore()
590 int32_t ShlConst = cast<ConstantSDNode>(Shl_1)->getSExtValue(); in SelectSHL()
597 int32_t ValConst = C->getSExtValue() << ShlConst; in SelectSHL()
613 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL) in SelectSHL()
618 int32_t ValConst = 1 << (ShlConst + C2->getSExtValue()); in SelectSHL()
753 unsigned Opc = (cast<ConstantSDNode>(N)->getSExtValue() != 0) in SelectConstant()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelDAGToDAG.cpp82 return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0); in canBeRepresentedAsSls()
105 int32_t Imm = CN->getSExtValue(); in INITIALIZE_PASS()
126 if (isInt<16>(CN->getSExtValue())) { in selectAddrRiSpls()
127 int16_t Imm = CN->getSExtValue(); in selectAddrRiSpls()
139 if (isInt<10>(CN->getSExtValue())) { in selectAddrRiSpls()
140 int16_t Imm = CN->getSExtValue(); in selectAddrRiSpls()
170 if ((RiMode && isInt<16>(CN->getSExtValue())) || in selectAddrRiSpls()
171 (!RiMode && isInt<10>(CN->getSExtValue()))) { in selectAddrRiSpls()
182 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i32); in selectAddrRiSpls()
256 if (isInt<16>(CN->getSExtValue())) in selectAddrRr()
H A DLanaiTargetTransformInfo.h68 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
72 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
73 if ((Imm.getSExtValue() & 0xFFFF) == 0) in getIntImmCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelDAGToDAG.cpp114 int32_t RHSC = RHS->getSExtValue(); in SelectAddrModeS9()
143 int32_t RHSC = RHS->getSExtValue(); in SelectAddrModeFar()
166 (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { in SelectFrameADDR_ri()
170 CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr), MVT::i32); in SelectFrameADDR_ri()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp211 Offset += C->getSExtValue(); in matchLSNode()
216 Offset -= C->getSExtValue(); in matchLSNode()
228 Offset += C->getSExtValue(); in matchLSNode()
236 Offset += C->getSExtValue(); in matchLSNode()
247 auto Off = C->getSExtValue(); in matchLSNode()
289 Offset += cast<ConstantSDNode>(Index->getOperand(1))->getSExtValue(); in matchLSNode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGIMatchTableExecutor.cpp35 return VRegVal->Value.getSExtValue() == Value; in isOperandImmEqual()
39 return VRegVal->getSExtValue() == Value; in isOperandImmEqual()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp54 int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue(); in INITIALIZE_PASS()
183 if (isIntN(12, CN->getSExtValue())) { in SelectInlineAsmMemoryOperand()
197 if (isIntN(16, CN->getSExtValue()) && in SelectInlineAsmMemoryOperand()
233 int64_t CVal = cast<ConstantSDNode>(Addr)->getSExtValue(); in SelectAddrConstant()
256 int64_t Imm = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue(); in SelectAddrRegImm12()
403 ImmValue.getSExtValue(), SDLoc(N), Subtarget->getGRLenVT()); in selectVSplatImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64GlobalISelUtils.cpp28 return RegOrConstant(ValAndVReg->Value.getSExtValue()); in getAArch64VectorSplat()
71 if (!Zero || Zero->Value.getSExtValue() != 0) in tryEmitBZero()
82 if (Size->Value.getSExtValue() <= 256) in tryEmitBZero()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelDAGToDAG.cpp152 if (isInt<32>(CN->getSExtValue())) { in selectADDRzii()
183 if (isInt<32>(CN->getSExtValue())) { in selectADDRzi()
235 if (isInt<32>(CN->getSExtValue())) { in matchADDRri()
274 bool BCTrueMask = (BConst->getSExtValue() != 0); in Select()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaSystemZ.cpp30 if (AbortCode->getSExtValue() >= 0 && AbortCode->getSExtValue() < 256) in CheckSystemZBuiltinFunctionCall()
H A DSemaM68k.cpp47 << AL << (int)MaybeNumParams->getSExtValue() in handleInterruptAttr()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp108 && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { in SelectADDRspii()
111 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr), in SelectADDRspii()
/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/PDB/Native/
H A DNativeSymbolEnumerator.cpp84 int64_t N = Record.Value.getSExtValue(); in getValue()
123 return Variant{Record.Value.getSExtValue()}; in getValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp534 int64_t Val = Cst->getSExtValue(); in tryShrinkShlLogicImm()
688 int32_t C1 = N1C->getSExtValue(); in trySignedBitfieldInsertInMask()
842 int64_t Offset = C->getSExtValue(); in tryIndexedLoad()
916 switch (LMulSDNode->getSExtValue()) { in selectSF_VC_X_SE()
1020 int64_t Imm = ConstNode->getSExtValue(); in Select()
1055 Imm = selectImm(CurDAG, DL, XLenVT, APF.bitcastToAPInt().getSExtValue(), in Select()
1375 bool IsCANDI = isInt<6>(N1C->getSExtValue()); in Select()
1600 bool Skip = C2 > 32 && isInt<12>(N1C->getSExtValue()) && in Select()
1647 if (isMask_64(C1) && !isInt<12>(N1C->getSExtValue())) { in Select()
1691 if (IsANDIOrZExt && (isInt<12>(N1C->getSExtValue()) || !N0.hasOneUse())) in Select()
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/freebsd/contrib/llvm-project/clang/lib/AST/ByteCode/
H A DIntegralAP.h54 return std::is_signed_v<T> ? Extended.getSExtValue() in truncateCast()
58 return std::is_signed_v<T> ? V.trunc(BitSize).getSExtValue() in truncateCast()
84 Val = V.getSExtValue(); in copy()
102 Val = Signed ? V.getSExtValue() : V.getZExtValue(); in IntegralAP()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp121 if (isInt<16>(CN->getSExtValue())) { in INITIALIZE_PASS()
128 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); in INITIALIZE_PASS()
148 if (isInt<16>(CN->getSExtValue())) { in SelectFIAddr()
155 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); in SelectFIAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h656 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15 in getFP16Imm()
694 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 in getFP32Imm()
722 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 in getFP64Imm()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp170 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost()
217 if (isInt<16>(Imm.getSExtValue())) in getIntImmCostInst()
224 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostInst()
238 if (isUInt<32>(-Imm.getSExtValue())) in getIntImmCostInst()
245 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostInst()
332 if (isUInt<32>(-Imm.getSExtValue())) in getIntImmCostIntrin()
340 if (isInt<32>(Imm.getSExtValue())) in getIntImmCostIntrin()
345 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
350 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp101 if (isInt<13>(CN->getSExtValue())) { in SelectADDRri()
110 Offset = CurDAG->getSignedTargetConstant(CN->getSExtValue(), in SelectADDRri()
140 if (isInt<13>(CN->getSExtValue())) in SelectADDRrr()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp572 int64_t RHSC = RHSDef->getOperand(1).getCImm()->getSExtValue(); in selectAddrRegImm()
729 int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue(); in select()
746 if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB)) in select()
761 if (!materializeImm(GPRRegHigh, Imm.extractBits(32, 32).getSExtValue(), in select()
764 if (!materializeImm(GPRRegLow, Imm.trunc(32).getSExtValue(), MIB)) in select()
891 int64_t CstVal = MI.getOperand(1).getCImm()->getSExtValue(); in renderNegImm()
918 int64_t CstVal = MI.getOperand(1).getCImm()->getSExtValue(); in renderImmPlus1()
952 int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue(); in renderAddiPairImmSmall()
962 int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue() < 0 ? -2048 : 2047; in renderAddiPairImmLarge()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp178 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
181 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
213 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) in getIntImmCostIntrin()
217 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
222 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) in getIntImmCostIntrin()
290 if (isInt<16>(Imm.getSExtValue())) in getIntImmCostInst()

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