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Searched refs:getRegSizeInBits (Results 1 – 25 of 61) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp336 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { in getCommonSuperRegClass()
344 unsigned MinSize = getRegSizeInBits(*RCA); in getCommonSuperRegClass()
352 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
361 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) in getCommonSuperRegClass()
370 if (getRegSizeInBits(*BestRC) == MinSize) in getCommonSuperRegClass()
494 TargetRegisterInfo::getRegSizeInBits(Register Reg, in getRegSizeInBits() function in TargetRegisterInfo
503 return getRegSizeInBits(*RC); in getRegSizeInBits()
512 return getRegSizeInBits(*RC); in getRegSizeInBits()
H A DImplicitNullChecks.cpp386 unsigned PointerRegSizeInBits = TRI->getRegSizeInBits(PointerReg, MRI); in isSuitableMemoryOp()
390 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp()
392 TRI->getRegSizeInBits(ScaledReg, MRI) != PointerRegSizeInBits)) in isSuitableMemoryOp()
423 int32_t RegSizeInBits = TRI->getRegSizeInBits(RegUsedInAddr, MRI); in isSuitableMemoryOp()
H A DRegisterBank.cpp44 assert(RBI.getMaximumSize(getID()) >= TRI.getRegSizeInBits(SubRC) && in verify()
H A DRegisterBankInfo.cpp509 return TRI.getRegSizeInBits(*RC); in getSizeInBits()
511 return TRI.getRegSizeInBits(Reg, MRI); in getSizeInBits()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.cpp133 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
140 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
147 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
154 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
172 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
H A DX86SpeculativeLoadHardening.cpp751 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCFG()
1180 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughIndirectBranches()
1557 .addImm(TRI->getRegSizeInBits(*PS->RC) - 1); in extractPredStateFromSP()
1862 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister()
1909 int Bytes = TRI->getRegSizeInBits(*RC) / 8; in hardenValueInRegister()
2180 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCall()
H A DX86TileConfig.cpp184 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp390 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64) && in shouldCoalesce()
397 unsigned SubregOpIdx = getRegSizeInBits(*SrcRC) == 128 ? 0 : 1; in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.h77 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) == in isLaneMaskReg()
H A DSIRegisterInfo.cpp621 unsigned NumRegs = divideCeil(getRegSizeInBits(*RC), 32); in getReservedRegs()
698 unsigned NumRegs = divideCeil(getRegSizeInBits(*RC), 32); in getReservedRegs()
712 unsigned NumRegs = divideCeil(getRegSizeInBits(*RC), 32); in getReservedRegs()
2882 unsigned Size = getRegSizeInBits(*SRC); in getEquivalentVGPRClass()
2890 unsigned Size = getRegSizeInBits(*SRC); in getEquivalentAGPRClass()
2898 unsigned Size = getRegSizeInBits(*VRC); in getEquivalentSGPRClass()
3034 unsigned SrcSize = getRegSizeInBits(*SrcRC); in shouldCoalesce()
3035 unsigned DstSize = getRegSizeInBits(*DstRC); in shouldCoalesce()
3036 unsigned NewSize = getRegSizeInBits(*NewRC); in shouldCoalesce()
3210 assert(getRegSizeInBits(*getPhysRegBaseClass(Reg)) <= 32); in get32BitRegister()
[all …]
H A DGCNRegPressure.cpp44 ? (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) in getRegKind()
46 ? (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) in getRegKind()
47 : (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
H A DSIFixSGPRCopies.cpp856 unsigned MoveSize = TRI->getRegSizeInBits(*SrcRC); in tryMoveVGPRConstToSGPR()
916 TRI->getRegSizeInBits(*DstRC)); in analyzeVGPRToSGPRCopy()
1065 size_t SrcSize = TRI->getRegSizeInBits(*SrcRC); in lowerVGPR2SGPRCopies()
1078 int N = TRI->getRegSizeInBits(*SrcRC) / 32; in lowerVGPR2SGPRCopies()
H A DSILowerI1Copies.cpp463 unsigned Size = TRI.getRegSizeInBits(Reg, MRI); in isVRegCompatibleReg()
693 assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32); in lowerCopiesToI1()
H A DGCNNSAReassign.cpp201 if (TRI->getRegSizeInBits(*MRI->getRegClass(Reg)) != 32 || Op.getSubReg()) in CheckNSA()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp193 unsigned SrcSize = TRI->getRegSizeInBits(Src, *MRI); in buildAnyextOrCopy()
194 unsigned DstSize = TRI->getRegSizeInBits(Dst, *MRI); in buildAnyextOrCopy()
585 unsigned SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); in lowerInlineAsm()
H A DInstructionSelect.cpp279 TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp271 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in spillCalleeSavedRegisters()
308 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in restoreCalleeSavedRegisters()
H A DAVRAsmPrinter.cpp129 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8; in PrintAsmOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp892 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
893 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp119 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32 in storeRegToStackSlot()
157 Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32 in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp338 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
339 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8; in printSavedRegsBitmask()
340 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; in printSavedRegsBitmask()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h297 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits() function
888 TypeSize getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp140 unsigned Num = TRI->getRegSizeInBits(Reg, MRI) / 32; in emitPrologue()
429 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves()

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