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Searched refs:getRegClassFor (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
328 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
339 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
340 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
477 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
488 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
H A DInstrEmitter.cpp107 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
212 const TargetRegisterClass *VTRC = TLI->getRegClassFor( in CreateVirtualRegisters()
275 const TargetRegisterClass *RC = TLI->getRegClassFor( in getVR()
419 ? TLI->getRegClassFor(OpVT, in AddOperand()
492 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
527 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
598 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
H A DFastISel.cpp321 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
806 CLI.ResultReg = createResultReg(TLI.getRegClassFor(ValueType)); in selectPatchpoint()
1573 const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty); in selectFreeze()
2235 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
H A DFunctionLoweringInfo.cpp372 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent)); in CreateReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DSwiftErrorValueTracking.cpp36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg()
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt()
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock()
240 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs()
H A DCallingConvLower.cpp253 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp394 Register MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
404 Register MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
430 Register DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
442 Register DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
502 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
591 Register NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
606 Register NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
657 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
966 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
978 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
[all …]
H A DARMISelLowering.h580 getRegClassFor(MVT VT, bool isDivergent = false) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp464 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in X86FastEmitLoad()
2034 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
2195 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
2338 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2365 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2435 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); in X86SelectIntToFP()
2494 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64)); in X86SelectFPExt()
2508 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32)); in X86SelectFPTrunc()
2610 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); in fastLowerIntrinsicCall()
2648 ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in fastLowerIntrinsicCall()
[all …]
H A DX86ISelLoweringCall.cpp1651 TargLowering.getRegClassFor(FR.VT)); in forwardMustTailParameters()
1846 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
H A DX86ISelDAGToDAG.cpp4976 unsigned RegClass = TLI->getRegClassFor(MaskVT)->getID(); in tryVPTESTM()
5014 unsigned RegClass = TLI->getRegClassFor(ResVT)->getID(); in tryVPTESTM()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1662 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1681 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1684 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicBinaryPartword()
1877 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicCmpSwap()
1929 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1932 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicCmpSwapPartword()
2560 Register Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
3707 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3777 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); in LowerFormalArguments()
4115 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
[all …]
H A DMipsSEISelDAGToDAG.cpp1305 TLI->getRegClassFor(ViaVecTy.getSimpleVT()); in trySelect()
1374 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); in trySelect()
H A DMipsFastISel.cpp1291 Register ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp408 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
421 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
439 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
575 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg); in fastMaterializeFloatZero()
2897 Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg); in selectIntToFP()
3614 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3773 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp513 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); in LowerCCCArguments()
1072 Register Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h553 const TargetRegisterClass *getRegClassFor(MVT VT,
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp736 const TargetRegisterClass *RC = getRegClassFor(MVT::i64); in EmitSubregExt()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1518 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); in finishCall()
1523 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1000 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
1037 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT)); in LowerFormalArguments()
3402 auto *ARClass = getRegClassFor(SPTy); in LowerDYNAMIC_STACKALLOC()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp1251 unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp712 getRegClassFor(MVT::i16)); in LowerCCCArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp648 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
2901 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp861 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
1207 Register Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1026 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {

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