Lines Matching refs:getRegClassFor

1662   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitSignExtendToI32InReg()
1681   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitAtomicBinaryPartword()
1684     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);  in emitAtomicBinaryPartword()
1877   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));  in emitAtomicCmpSwap()
1929   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);  in emitAtomicCmpSwapPartword()
1932     getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);  in emitAtomicCmpSwapPartword()
2560   Register Reg = MF.addLiveIn(RA, getRegClassFor(VT));  in lowerRETURNADDR()
3707       const TargetRegisterClass *RC = getRegClassFor(RegVT);  in LowerFormalArguments()
3777             getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));  in LowerFormalArguments()
4115     RC = getRegClassFor(VT);  in parseRegForInlineAsmConstraint()
4124     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);  in parseRegForInlineAsmConstraint()
4127     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);  in parseRegForInlineAsmConstraint()
4402   const TargetRegisterClass *RC = getRegClassFor(RegTy);  in copyByValRegs()
4521   const TargetRegisterClass *RC = getRegClassFor(RegTy);  in writeVarArgRegs()