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Searched refs:getNode (Results 1 – 25 of 212) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp646 const auto Flags = Op.getNode()->getFlags(); in mayIgnoreSignedZero()
935 if (!allUsesHaveSourceMods(Op.getNode())) in getNegatedExpression()
947 return DAG.getNode(AMDGPUISD::RCP, SL, VT, NegSrc, Op->getFlags()); in getNegatedExpression()
1332 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain); in LowerReturn()
1364 for (SDNode *U : DAG.getEntryNode().getNode()->users()) { in addTokenForArgument()
1381 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in addTokenForArgument()
1544 SDValue Trap = DAG.getNode(ISD::TRAP, DL, MVT::Other, DAG.getEntryNode()); in LowerGlobalAddress()
1545 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, in LowerGlobalAddress()
1579 SDValue NewIn = DAG.getNode(ISD::BITCAST, SL, NewEltVT, In); in LowerCONCAT_VECTORS()
1589 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
[all …]
H A DAMDGPUHSAMetadataStreamer.cpp206 Dims.push_back(Dims.getDocument()->getNode( in getWorkGroupDimensions()
213 Version.push_back(Version.getDocument()->getNode(VersionMajorV4)); in emitVersion()
214 Version.push_back(Version.getDocument()->getNode(VersionMinorV4)); in emitVersion()
221 HSAMetadataDoc->getNode(TargetID.toString(), /*Copy=*/true); in emitTargetID()
232 Printf.push_back(Printf.getDocument()->getNode( in emitPrintf()
247 Kern[".language"] = Kern.getDocument()->getNode("OpenCL C"); in emitKernelLanguage()
249 LanguageVersion.push_back(Kern.getDocument()->getNode( in emitKernelLanguage()
251 LanguageVersion.push_back(Kern.getDocument()->getNode( in emitKernelLanguage()
265 Kern[".vec_type_hint"] = Kern.getDocument()->getNode( in emitKernelAttrs()
275 Kern.getDocument()->getNode(std::move(HandleName), /*Copy=*/true); in emitKernelAttrs()
[all …]
H A DR600ISelLowering.cpp418 assert((!Result.getNode() || in LowerOperation()
419 Result.getNode()->getNumValues() == 2) && in LowerOperation()
445 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
494 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
508 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp219 if (MemSDNode *MemN = dyn_cast<MemSDNode>(Op.getNode())) in getNodeChain()
231 if (auto *MemN = dyn_cast<MemSDNode>(Op.getNode())) in getMemoryPtr()
300 if (auto *StoreN = dyn_cast<VPStridedStoreSDNode>(Op.getNode())) in getLoadStoreStride()
302 if (auto *StoreN = dyn_cast<VPStridedLoadSDNode>(Op.getNode())) in getLoadStoreStride()
305 if (isa<MemSDNode>(Op.getNode())) { in getLoadStoreStride()
308 uint64_t ElemStride = getIdiomaticVectorType(Op.getNode()) in getLoadStoreStride()
317 if (auto *N = dyn_cast<MaskedGatherScatterSDNode>(Op.getNode())) in getGatherScatterIndex()
319 if (auto *N = dyn_cast<VPGatherScatterSDNode>(Op.getNode())) in getGatherScatterIndex()
325 if (auto *N = dyn_cast<MaskedGatherScatterSDNode>(Op.getNode())) in getGatherScatterScale()
327 if (auto *N = dyn_cast<VPGatherScatterSDNode>(Op.getNode())) in getGatherScatterScale()
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H A DVVPISelLowering.cpp33 auto LoRes = CDAG.getNode(Opc, MVT::v256i1, {LoA, LoB}); in splitMaskArithmetic()
34 auto HiRes = CDAG.getNode(Opc, MVT::v256i1, {HiA, HiB}); in splitMaskArithmetic()
59 EVT OpVecVT = *getIdiomaticVectorType(Op.getNode()); in lowerToVVP()
84 return CDAG.getNode(VVPOpcode, LegalVecVT, {Op->getOperand(0), Mask, AVL}); in lowerToVVP()
86 return CDAG.getNode(VVPOpcode, LegalVecVT, in lowerToVVP()
105 return CDAG.getNode(VVPOpcode, LegalVecVT, {X, Y, Z, Mask, AVL}); in lowerToVVP()
111 return CDAG.getNode(VVPOpcode, LegalVecVT, {OnTrue, OnFalse, Mask, AVL}); in lowerToVVP()
118 return CDAG.getNode(VVPOpcode, LegalResVT, {LHS, RHS, Pred, Mask, AVL}); in lowerToVVP()
140 auto DataVT = *getIdiomaticVectorType(Op.getNode()); in lowerVVP_LOAD_STORE()
155 auto NewLoadV = CDAG.getNode(VEIS in lowerVVP_LOAD_STORE()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/BinaryFormat/
H A DMsgPackDocument.cpp31 return find(getDocument()->getNode(S)); in find()
37 return (*this)[getDocument()->getNode(S)]; in operator []()
53 return (*this)[getDocument()->getNode(Key)]; in operator []()
56 return (*this)[getDocument()->getNode(Key)]; in operator []()
59 return (*this)[getDocument()->getNode(Key)]; in operator []()
62 return (*this)[getDocument()->getNode(Key)]; in operator []()
80 *this = getDocument()->getNode(Val); in operator =()
84 *this = getDocument()->getNode(Val); in operator =()
88 *this = getDocument()->getNode(Val); in operator =()
92 *this = getDocument()->getNode(Va in operator =()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp456 NewLHS = DAG.getNode(ISD::AssertZext, dl, RetVT, Call.first, in softenSetCCOperands()
467 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Call.second, in softenSetCCOperands()
469 NewLHS = DAG.getNode(ShouldInvertCC ? ISD::AND : ISD::OR, dl, in softenSetCCOperands()
508 return DAG.getNode(ISD::BRIND, dl, MVT::Other, Chain, Addr); in expandIndirectJTBranch()
550 return TLO.New.getNode(); in ShrinkDemandedConstant()
571 SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC, in ShrinkDemandedConstant()
602 assert(Op.getNode()->getNumValues() == 1 && in ShrinkDemandedOp()
619 if (!Op.getNode()->hasOneUse()) in ShrinkDemandedOp()
635 SDValue X = DAG.getNode( in ShrinkDemandedOp()
637 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), in ShrinkDemandedOp()
[all …]
H A DDAGCombiner.cpp733 if (ISD::isBuildVectorOfConstantSDNodes(StoreVal.getNode()) || in getStoreSource()
734 ISD::isBuildVectorOfConstantFPSDNodes(StoreVal.getNode())) in getStoreSource()
968 AddToWorklist(Op.getNode()); in deleteAndRecombine()
1082 ISD::isBuildVectorOfConstantFPSDNodes(V.getNode()); in isAnyConstantBuildVector()
1128 LoadStore && LoadStore->getBasePtr().getNode() == N) { in reassociationCanBreakAddressingModePattern()
1235 return DAG.getNode(Opc, DL, VT, N00, OpNode, NewFlags); in reassociateOpsCommutative()
1242 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags); in reassociateOpsCommutative()
1243 return DAG.getNode(Opc, DL, VT, OpNode, N01, NewFlags); in reassociateOpsCommutative()
1272 return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N01); in reassociateOpsCommutative()
1282 return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N00); in reassociateOpsCommutative()
[all …]
H A DLegalizeTypesGeneric.cpp58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
96 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
97 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
H A DLegalizeIntegerTypes.cpp363 if (Res.getNode()) in PromoteIntegerResult()
376 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
383 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
493 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
497 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
500 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp)); in PromoteIntRes_BITCAST()
504 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
513 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
530 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
534 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
[all …]
H A DLegalizeDAG.cpp242 UpdatedNodes->insert(New.getNode()); in ReplaceNode()
243 ReplacedNode(Old.getNode()); in ReplaceNode()
254 UpdatedNodes->insert(New[i].getNode()); in ReplaceNode()
265 UpdatedNodes->insert(New.getNode()); in ReplaceNodeWithValue()
266 ReplacedNode(Old.getNode()); in ReplaceNodeWithValue()
404 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
480 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); in OptimizeFloatStore()
498 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { in LegalizeStoreOps()
532 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
586 Hi = DAG.getNode( in LegalizeStoreOps()
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H A DResourcePriorityQueue.cpp74 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
112 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
131 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU()
239 if (!SU || !SU->getNode()) in isResourceAvailable()
244 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
249 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
250 switch (SU->getNode()->getMachineOpcode()) { in isResourceAvailable()
253 SU->getNode()->getMachineOpcode()))) in isResourceAvailable()
284 if (!isResourceAvailable(SU) || SU->getNode()->getGluedNode()) { in reserveResources()
289 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
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H A DMatchContext.h36 template <typename... ArgT> SDValue getNode(ArgT &&...Args) { in getNode() function
37 return DAG.getNode(std::forward<ArgT>(Args)...); in getNode()
97 !ISD::isConstantSplatVectorAllOnes(MaskOp.getNode())) in match()
112 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode() function
116 return DAG.getNode(VPOpcode, DL, VT, in getNode()
120 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() function
125 return DAG.getNode(VPOpcode, DL, VT, {N1, N2, RootMaskOp, RootVectorLenOp}); in getNode()
128 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() function
133 return DAG.getNode(VPOpcode, DL, VT, in getNode()
137 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, in getNode() function
[all …]
H A DLegalizeVectorTypes.cpp242 if (R.getNode()) in ScalarizeVectorResult()
249 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_BinOp()
268 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_CMP()
276 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1, in ScalarizeVecRes_TernaryOp()
284 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1, in ScalarizeVecRes_FIX()
300 DAG.getNode(N->getOpcode(), dl, in ScalarizeVecRes_UnaryOpWithTwoResults()
302 .getNode(); in ScalarizeVecRes_UnaryOpWithTwoResults()
310 SDValue OtherVal = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, OtherVT, in ScalarizeVecRes_UnaryOpWithTwoResults()
346 SDValue Result = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(ValueVTs), in ScalarizeVecRes_StrictFPOp()
375 SDNode *ScalarNode = DAG.getNode( in ScalarizeVecRes_OverflowOp()
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H A DLegalizeVectorOps.cpp284 SDNode *Node = DAG.UpdateNodeOperands(Op.getNode(), Ops); in LegalizeOp()
600 if (!Res.getNode()) in LowerOperationWrapper()
635 Operands[0] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(0)); in PromoteSETCC()
636 Operands[1] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(1)); in PromoteSETCC()
644 SDValue Res = DAG.getNode(Node->getOpcode(), DL, Node->getSimpleValueType(0), in PromoteSETCC()
668 DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {NewVecVT, MVT::Other}, in PromoteSTRICT()
677 Operands[0] = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in PromoteSTRICT()
680 DAG.getNode(Node->getOpcode(), DL, VTs, Operands, Node->getFlags()); in PromoteSTRICT()
683 DAG.getNode(ISD::STRICT_FP_ROUND, DL, {VecVT, MVT::Other}, in PromoteSTRICT()
699 SDValue NewOp = DAG.getNode(ISD::FP_EXTEND, DL, NewOpVT, Node->getOperand(0)); in PromoteFloatVECREDUCE()
[all …]
H A DSelectionDAGBuilder.cpp204 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
205 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
211 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
225 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); in getCopyFromParts()
226 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, in getCopyFromParts()
230 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); in getCopyFromParts()
231 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); in getCopyFromParts()
238 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
239 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
242 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp181 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); in LowerOperation()
221 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
226 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
228 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
260 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); in LowerGlobalAddress()
283 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result); in LowerBlockAddress()
301 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
323 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
326 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, in LowerBR_JT()
328 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, in LowerBR_JT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp513 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
560 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
738 return DAG.getNode(ISD::SHL, dl, MVT::i32, in convertToByteIndex()
754 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32()
825 if (!SplatV.getNode()) in buildHvxVectorReg()
841 assert(SplatV.getNode()); in buildHvxVectorReg()
845 SDValue S = DAG.getNode(ISD::SPLAT_VECTOR, dl, WordTy, SplatV); in buildHvxVectorReg()
883 if (Vec.getNode() != nullptr && T.getNode() != Vec.getNode()) in buildHvxVectorReg()
953 SDValue SplatV = DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Words[n]); in buildHvxVectorReg()
954 HalfV = DAG.getNode(HexagonISD::VALIGN, dl, VecTy, in buildHvxVectorReg()
[all …]
H A DHexagonISelDAGToDAG.cpp80 int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue(); in INITIALIZE_PASS()
252 SelectStore(TS.getNode()); in StoreInstrForLoadIntrinsic()
253 StoreN = Handle.getValue().getNode(); in StoreInstrForLoadIntrinsic()
283 SDNode *C = Ch.getNode(); in tryLoadOfLoadIntrinsic()
311 if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(3).getNode()) in tryLoadOfLoadIntrinsic()
480 int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue(); in SelectIndexedStore()
699 SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), in SelectIntrinsicWOChain()
701 ReplaceNode(N, R.getNode()); in SelectIntrinsicWOChain()
702 SelectCode(R.getNode()); in SelectIntrinsicWOChain()
723 ReplaceNode(N, Ext.getNode()); in SelectExtractSubvector()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp168 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, Arg.ArgVT, Value); in handleCMSEValue()
170 DAG.getNode(Arg.Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, in handleCMSEValue()
2168 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()), in MoveToHPR()
2171 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val); in MoveToHPR()
2173 Val = DAG.getNode(ISD::TRUNCATE, dl, in MoveToHPR()
2175 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val); in MoveToHPR()
2184 Val = DAG.getNode(ARMISD::VMOVrh, dl, in MoveFromHPR()
2187 Val = DAG.getNode(ISD::BITCAST, dl, in MoveFromHPR()
2189 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, in MoveFromHPR()
2192 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val); in MoveFromHPR()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2401 isIntImmediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
2485 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0), in optimizeLogicalImm()
3214 N = N->getOperand(0).getNode(); in isZerosVector()
3436 LHS = DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other}, in emitStrictFPComparison()
3438 RHS = DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other}, in emitStrictFPComparison()
3444 return DAG.getNode(Opcode, DL, {MVT::i32, MVT::Other}, {Chain, LHS, RHS}); in emitStrictFPComparison()
3455 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitComparison()
3456 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitComparison()
3458 return DAG.getNode(AArch64ISD::FCMP, DL, MVT::i32, LHS, RHS); in emitComparison()
3483 DAG.getNode(AArch64ISD::ANDS, DL, DAG.getVTList(VT, MVT_CC), in emitComparison()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2780 if (!ISD::isNormalLoad(Op.getNode())) in mayFoldLoad()
2784 auto *Ld = cast<LoadSDNode>(Op.getNode()); in mayFoldLoad()
2804 auto *Ld = cast<LoadSDNode>(Op.getNode()); in mayFoldLoadIntoBroadcastFromMem()
2824 unsigned Opcode = Op.getNode()->user_begin()->getOpcode(); in mayFoldIntoZeroExtend()
3014 if (ISD::isNON_EXTLoad(LHS.getNode()) && in TranslateX86CC()
3015 !ISD::isNON_EXTLoad(RHS.getNode())) { in TranslateX86CC()
3344 if (!ISD::isConstantSplatVector(C.getNode(), MulC)) in decomposeMulByConstant()
4283 if (collectConcatOps(Lo.getNode(), LoOps, DAG) && in collectConcatOps()
4284 collectConcatOps(Hi.getNode(), HiOps, DAG) && in collectConcatOps()
4318 if (collectConcatOps(Src.getNode(), SrcOps, DAG) && in collectConcatOps()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp342 if (Result.getNode()) { in LowerAsmOperandForConstraint()
458 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
461 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
465 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
507 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); in LowerCCCArguments()
583 if (Glue.getNode()) in LowerReturn()
587 return DAG.getNode(Opc, DL, MVT::Other, in LowerReturn()
664 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
667 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
670 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp410 return SDValue(OutRetAddr.getNode(), 1); in EmitTailCallLoadRetAddr()
496 return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val) in LowerMemArgument()
508 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerMemOpCallTo()
659 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
662 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
665 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
686 if (!StackPtr.getNode()) { in LowerCall()
696 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall()
744 if (!StackPtr.getNode()) { in LowerCall()
748 Source = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp195 auto It = Regs.find(MsgPackDoc.getNode(Reg)); in getRegister()
213 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; in setRegister()
216 N = N.getDocument()->getNode(Val); in setRegister()
229 auto &N = getRegisters()[MsgPackDoc.getNode(Reg)]; in setRegister()
261 MsgPackDoc.getNode(Name, /*Copy=*/true); in setEntryPoint()
271 MsgPackDoc.getNode(EPNameOS.str(), /*Copy=*/true); in setEntryPoint()
289 getHwStage(CC)[".vgpr_count"] = MsgPackDoc.getNode(Val); in setNumUsedVgprs()
328 getHwStage(CC)[".sgpr_count"] = MsgPackDoc.getNode(Val); in setNumUsedSgprs()
353 getHwStage(CC)[".scratch_memory_size"] = MsgPackDoc.getNode(Val); in setScratchSize()
370 Node[".stack_frame_size_in_bytes"] = MsgPackDoc.getNode(Val); in setFunctionScratchSize()
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