Lines Matching refs:getNode
414 assert((!Result.getNode() || in LowerOperation()
415 Result.getNode()->getNumValues() == 2) && in LowerOperation()
441 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
490 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
508 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
511 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
564 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
567 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1)); in LowerOperation()
629 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, in vectorToVerticalVector()
633 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
647 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
663 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
680 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(GSD), ConstPtrVT, GA); in LowerGlobalAddress()
691 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
692 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
693 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
707 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
708 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
713 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
720 expandShiftParts(Op.getNode(), Lo, Hi, DAG); in LowerShiftParts()
732 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
734 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
737 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
739 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
744 return DAG.getNode( in lowerFP_TO_UINT()
754 return DAG.getNode( in lowerFP_TO_SINT()
851 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
892 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
893 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
908 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
912 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
932 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
934 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
981 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1043 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1048 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1059 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1063 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1068 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1075 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1079 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1086 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1089 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1098 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1126 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1146 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr, in LowerSTORE()
1163 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr, in LowerSTORE()
1165 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1169 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1172 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1173 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1191 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1212 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1275 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1280 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1289 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1293 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1297 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1304 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1353 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1354 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1361 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1384 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1398 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1399 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1410 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(), in LowerBRCOND()
1569 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in CompactSwizzlableVector()
1614 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in ReorganizeVector()
1690 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in constBufferLoad()
1692 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1702 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1726 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
1751 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1786 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
1787 InVec.getNode()->op_end()); in PerformDAGCombine()
1802 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1803 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
1827 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
1854 if (LHS.getOperand(2).getNode() != True.getNode() || in PerformDAGCombine()
1855 LHS.getOperand(3).getNode() != False.getNode() || in PerformDAGCombine()
1856 RHS.getNode() != False.getNode()) { in PerformDAGCombine()
1896 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
1925 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
1953 if (!Neg.getNode()) in FoldOperand()
1959 if (!Abs.getNode()) in FoldOperand()
1968 if (!Sel.getNode()) in FoldOperand()
2055 if (!Imm.getNode()) in FoldOperand()