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Searched refs:getLocReg (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp122 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
173 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
174 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
178 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
179 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
295 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
342 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
343 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
H A DARMFastISel.cpp2043 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
2044 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2057 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
2058 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
2060 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2061 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2107 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2108 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2110 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2111 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp748 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); in Passv64i1ArgInRegs()
749 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Hi)); in Passv64i1ArgInRegs()
783 MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg()); in LowerReturn()
807 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(VA.getLocReg())) { in LowerReturn()
811 X86::FR64XRegClass.contains(VA.getLocReg()) && in LowerReturn()
821 if (VA.getLocReg() == X86::FP0 || in LowerReturn()
822 VA.getLocReg() == X86::FP1) { in LowerReturn()
827 RetVals.push_back(std::make_pair(VA.getLocReg(), ValToCopy)); in LowerReturn()
836 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
857 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg()); in LowerReturn()
[all …]
H A DX86FastISel.cpp1240 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1269 Register DstReg = VA.getLocReg(); in X86SelectRet()
1278 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
3479 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
3480 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3634 Register SrcReg = VA.getLocReg(); in fastLowerCall()
3653 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp177 auto CopyLo = MIRBuilder.buildCopy(LLT::scalar(32), VALo.getLocReg()); in assignCustomValue()
178 auto CopyHi = MIRBuilder.buildCopy(LLT::scalar(32), VAHi.getLocReg()); in assignCustomValue()
186 markPhysRegUsed(VALo.getLocReg()); in assignCustomValue()
187 markPhysRegUsed(VAHi.getLocReg()); in assignCustomValue()
283 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
284 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
288 MIRBuilder.buildCopy(VALo.getLocReg(), Lo); in assignCustomValue()
289 MIRBuilder.buildCopy(VAHi.getLocReg(), Hi); in assignCustomValue()
H A DMipsFastISel.cpp1237 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1238 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1308 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1309 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1734 Register DestReg = VA.getLocReg(); in selectRet()
1775 RetRegs.push_back(VA.getLocReg()); in selectRet()
H A DMipsISelLowering.cpp3487 Register LocRegLo = VA.getLocReg(); in LowerCall()
3488 Register LocRegHigh = ArgLocs[++i].getLocReg(); in LowerCall()
3529 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
3533 if (Mips::AFGR64RegClass.contains(VA.getLocReg())) in LowerCall()
3539 CSInfo.ArgRegPairs.emplace_back(VA.getLocReg(), i); in LowerCall()
3697 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
3864 Register ArgReg = VA.getLocReg(); in LowerFormalArguments()
3886 addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC); in LowerFormalArguments()
4054 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
4058 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCallingConvLower.cpp77 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
230 Regs.push_back(Locs[I].getLocReg()); in getRemainingRegParmsForType()
284 return Loc1.getLocReg() == Loc2.getLocReg(); in resultsCompatible()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp108 Register PhysReg = VA.getLocReg(); in assignCustomValue()
152 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
154 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi); in assignCustomValue()
245 Register PhysReg = VA.getLocReg(); in assignCustomValue()
281 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
283 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi); in assignCustomValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp255 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
308 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); in unpack64()
311 if (VA.getLocReg() == CSKY::R3) { in unpack64()
320 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); in unpack64()
469 Register RegLo = VA.getLocReg(); in LowerReturn()
482 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
486 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
586 Register RegLo = VA.getLocReg(); in LowerCall()
614 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
725 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp303 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Glue); in LowerReturn_32()
305 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
307 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
310 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Glue); in LowerReturn_32()
314 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
397 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
405 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Glue); in LowerReturn_64()
409 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
473 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
486 Register loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp308 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
402 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue); in lowerCallResult()
515 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCallArguments()
687 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
692 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp382 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
508 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
615 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
620 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
653 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp941 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
944 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
1149 MCRegister PhysReg = ArgLoc.getLocReg(); in parametersInCSRMatch()
1230 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp534 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
645 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
651 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
731 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
827 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp451 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
554 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
558 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
683 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
778 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp461 if (Subtarget.isWindowedABI() && (VA.getLocReg() == FrameReg)) { in LowerFormalArguments()
465 Reg = MF.addLiveIn(VA.getLocReg(), &Xtensa::ARRegClass); in LowerFormalArguments()
621 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
752 unsigned Reg = VA.getLocReg(); in LowerCall()
802 unsigned Register = VA.getLocReg(); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp951 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1044 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1191 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1375 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
1380 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h129 Register getLocReg() const { return std::get<Register>(Data); } in getLocReg() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1356 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1511 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1617 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), in LowerCallResult()
1674 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Glue); in LowerReturn()
1678 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp683 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
901 Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InGlue) in LowerCallResult()
955 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
1113 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Glue); in LowerReturn()
1115 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
1340 Register Reg = VA.getLocReg(); in IsEligibleForTailCallOptimization()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp320 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Glue); in LowerReturn()
324 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
445 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
459 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
591 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
951 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
952 HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg()); in LowerFormalArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp423 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Glue); in LowerReturn()
427 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
468 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); in LowerFormalArguments()
714 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
792 Register Reg = VA.getLocReg(); in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4352 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
4353 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC); in LowerFormalArguments_32SVR4()
4361 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
5381 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5386 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5395 VA.getLocReg(), VA.getLocVT(), InGlue); in LowerCallResult()
6162 RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0))); in LowerCall_32SVR4()
6165 RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(), in LowerCall_32SVR4()
6168 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
7258 const Register VReg = MF.addLiveIn(VA.getLocReg(), RegClass); in LowerFormalArguments_AIX()
[all …]
H A DPPCFastISel.cpp1503 Register SourcePhysReg = VA.getLocReg(); in finishCall()
1710 Register RetReg = VA.getLocReg(); in SelectRet()
1734 RetRegs.push_back(VA.getLocReg()); in SelectRet()

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