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Searched refs:getInstr (Results 1 – 25 of 102) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp31 if (QII->mayBeCurLoad(*SUd->getInstr())) in hasDependence()
34 if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
57 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) { in SchedulingCost()
H A DHexagonSubtarget.cpp264 MachineInstr &MI1 = *SU.getInstr(); in apply()
273 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
301 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
305 unsigned Type = HII.getType(*Inst2.getInstr()); in shouldTFRICallBind()
325 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
328 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
349 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
389 MachineInstr &L0 = *S0.getInstr(); in apply()
403 MachineInstr &L1 = *S1.getInstr(); in apply()
442 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
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H A DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
98 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
113 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
166 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
H A DHexagonVLIWPacketizer.cpp423 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
517 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
518 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
519 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
674 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
760 MachineInstr &TempMI = *TempSU->getInstr(); in canPromoteToNewValueStore()
773 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
827 MachineInstr &PacketMI = *PacketSU->getInstr(); in canPromoteToNewValue()
860 const MachineInstr &PI = *PacketSU->getInstr(); in canPromoteToDotNew()
1326 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
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H A DHexagonISelLoweringHVX.cpp1027 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in createHvxPrefixPred()
1190 return getInstr(Hexagon::C2_cmpgtui, dl, MVT::i1, {ExtB, Zero}, DAG); in extractHvxElementPred()
1354 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy, in extractHvxSubvectorPred()
1479 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in insertHvxSubvectorPred()
1481 ByteVec = getInstr(Hexagon::V6_vmux, dl, ByteTy, {Q, ByteSub, ByteVec}, DAG); in insertHvxSubvectorPred()
1548 SDValue Vrmpy = getInstr(Hexagon::V6_vrmpyub, dl, ByteTy, {Sel, All1}, DAG); in compressHvxPred()
1550 SDValue Rot = getInstr(Hexagon::V6_valignbi, dl, ByteTy, in compressHvxPred()
2199 SDValue Store = getInstr(StoreOpc, dl, MVT::Other, in LowerHvxMaskedOp()
2211 SDValue LoV = getInstr(Hexagon::V6_vlalignb, dl, ty(V), {V, Z, A}, DAG); in LowerHvxMaskedOp()
2212 SDValue HiV = getInstr(Hexago in LowerHvxMaskedOp()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.cpp308 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
311 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
312 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
313 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
318 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
323 Pred.getInstr()->getDebugExpression()); in beginFunction()
330 if (IsDescribedByReg(I->getInstr())) in beginFunction()
332 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
339 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
341 requestLabelAfterInsn(Entry.getInstr()); in beginFunction()
H A DDbgEntityHistoryCalculator.cpp79 Entries.back().getInstr()->isEquivalentDbgInstr(MI)) { in startDbgValue()
81 << "\t" << Entries.back().getInstr() << "\t" << MI in startDbgValue()
95 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) in startClobber()
200 const MachineInstr *StartMI = EI->getInstr(); in trimLocationRanges()
202 ? HistoryMapEntries[EndIndex].getInstr() in trimLocationRanges()
271 const MachineInstr *MI = Entry.getInstr(); in hasNonEmptyLocation()
345 if (Entry.getInstr()->isDebugEntryValue()) in clobberRegEntries()
347 if (Entry.getInstr()->hasDebugOperandForReg(RegNo)) { in clobberRegEntries()
350 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
354 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUIGroupLP.cpp204 << *SU.getInstr()); in add()
245 assert(SU.getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER || in resetEdges()
246 SU.getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER || in resetEdges()
247 SU.getInstr()->getOpcode() == AMDGPU::IGLP_OPT); in resetEdges()
398 return SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER; in reset()
456 if (SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) in makePipeline()
951 if (TII->isMFMAorWMMA(*I->getInstr())) in apply()
988 if (FoundTrans && TII->isMFMAorWMMA(*I->getInstr())) { in apply()
995 if (!FoundTrans && TII->isTRANS(I->getInstr()->getOpcode())) in apply()
1022 if (!SU || !TII->isMFMAorWMMA(*ChainSeed->getInstr())) in apply()
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H A DR600MachineScheduler.cpp154 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
155 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
188 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
211 MachineInstr *MI = SU->getInstr(); in getAluKind()
285 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
314 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
316 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
384 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
433 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
H A DGCNDPPCombine.cpp247 if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) { in createDPPInst()
293 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
326 if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) { in createDPPInst()
346 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
347 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
426 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
429 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
430 return DPPInst.getInstr(); in createDPPInst()
620 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
H A DSIMachineScheduler.cpp250 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
317 RPTracker.setPos(SU->getInstr()); in initRegPressure()
398 TopRPTracker.setPos(SU->getInstr()); in schedule()
1117 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1129 if (!SIInstrInfo::isEXP(*SuccSU->getInstr())) { in colorExports()
1314 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1343 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1785 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1795 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1816 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
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H A DAMDGPUExportClustering.cpp30 return SIInstrInfo::isEXP(*SU.getInstr()); in isExport()
34 const MachineInstr *MI = SU->getInstr(); in isPositionExport()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp93 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
94 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
175 if (DAG->ExitSU.getInstr()) in scheduleAdjacentImpl()
183 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
202 const MachineInstr *DepMI = DepSU.getInstr(); in createMacroFusionDAGMutation()
H A DMachinePipeliner.cpp710 OrderedInsts.push_back(SU->getInstr()); in schedule()
711 Cycles[SU->getInstr()] = Cycle; in schedule()
712 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
843 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
868 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
944 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
999 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
1001 if (I.getInstr()->isPHI()) { in updatePhiDependences()
1024 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, in changeDependences()
1029 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg(); in changeDependences()
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H A DVLIWMachineScheduler.cpp109 if (!SU || !SU->getInstr()) in isResourceAvailable()
114 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
116 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
162 switch (SU->getInstr()->getOpcode()) { in reserveResources()
164 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
186 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
326 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
365 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
432 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
532 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta, in readyQueueVerboseDump()
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H A DScheduleDAGInstrs.cpp239 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
248 const MCInstrDesc &DefMIDesc = SU->getInstr()->getDesc(); in addPhysRegDataDeps()
271 UseInstr = UseSU->getInstr(); in addPhysRegDataDeps()
280 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
295 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
317 MachineInstr *DefInstr = DefSU->getInstr(); in addPhysRegDeps()
405 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
453 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
500 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
525 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
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H A DSlotIndexes.cpp137 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
150 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
220 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
261 if (ILE.getInstr()) in print()
262 OS << *ILE.getInstr(); in print()
H A DMachineScheduler.cpp868 MachineInstr *MI = SU->getInstr(); in schedule()
1194 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1385 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); in updatePressureDiffs()
1414 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in updatePressureDiffs()
1419 << *SU->getInstr(); in updatePressureDiffs()
1430 if (EntrySU.getInstr() != nullptr) in dump()
1439 if (SchedModel.mustBeginGroup(SU.getInstr()) && in dump()
1440 SchedModel.mustEndGroup(SU.getInstr())) in dump()
1446 if (ExitSU.getInstr() != nullptr) in dump()
1611 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in computeCyclicCriticalPath()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp363 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVI()
409 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n'); in ExpandMOVX_RR()
412 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n"); in ExpandMOVX_RR()
424 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVSZX_RR()
456 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc); in ExpandMOVSZX_RR()
461 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
464 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
475 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and "); in ExpandMOVSZX_RM()
493 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandMOVSZX_RM()
511 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandPUSH_POP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp47 MachineInstr *MI = SU->getInstr(); in getHazardType()
90 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
185 MachineInstr &L0 = *SU->getInstr(); in getHazardType()
257 MachineInstr &MI = *SU->getInstr(); in EmitInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp66 MachineInstr *Instr0 = TryCand.SU->getInstr(); in tryCandidate()
67 MachineInstr *Instr1 = Cand.SU->getInstr(); in tryCandidate()
H A DAArch64Subtarget.cpp487 (Def->getInstr()->getOpcode() != TargetOpcode::BUNDLE && in adjustSchedDependency()
488 Use->getInstr()->getOpcode() != TargetOpcode::BUNDLE)) in adjustSchedDependency()
493 const MachineInstr *DefMI = Def->getInstr(); in adjustSchedDependency()
505 const MachineInstr *UseMI = Use->getInstr(); in adjustSchedDependency()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86WinFixupBufferSecurityCheck.cpp165 return std::make_pair(CMI.getInstr(), JMI.getInstr()); in CreateFailCheckSequence()
236 MachineBasicBlock::iterator SplicePt(JMI.getInstr()); in runOnMachineFunction()

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