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Searched refs:getInstr (Results 1 – 25 of 107) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp31 if (QII->mayBeCurLoad(*SUd->getInstr())) in hasDependence()
34 if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
57 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) { in SchedulingCost()
H A DHexagonSubtarget.cpp263 MachineInstr &MI1 = *SU.getInstr(); in apply()
272 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
300 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
304 unsigned Type = HII.getType(*Inst2.getInstr()); in shouldTFRICallBind()
324 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
327 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
348 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
390 MachineInstr &L0 = *S0.getInstr(); in apply()
404 MachineInstr &L1 = *S1.getInstr(); in apply()
443 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
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H A DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
98 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
113 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
166 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
H A DHexagonVLIWPacketizer.cpp414 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
508 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
509 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
510 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
665 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
751 MachineInstr &TempMI = *TempSU->getInstr(); in canPromoteToNewValueStore()
764 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
818 MachineInstr &PacketMI = *PacketSU->getInstr(); in canPromoteToNewValue()
851 const MachineInstr &PI = *PacketSU->getInstr(); in canPromoteToDotNew()
1317 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.cpp312 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
315 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
316 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
317 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
322 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
327 Pred.getInstr()->getDebugExpression()); in beginFunction()
334 if (IsDescribedByReg(I->getInstr())) in beginFunction()
336 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
343 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
345 requestLabelAfterInsn(Entry.getInstr()); in beginFunction()
H A DDbgEntityHistoryCalculator.cpp79 Entries.back().getInstr()->isEquivalentDbgInstr(MI)) { in startDbgValue()
81 << "\t" << Entries.back().getInstr() << "\t" << MI in startDbgValue()
95 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) in startClobber()
200 const MachineInstr *StartMI = EI->getInstr(); in trimLocationRanges()
202 ? HistoryMapEntries[EndIndex].getInstr() in trimLocationRanges()
271 const MachineInstr *MI = Entry.getInstr(); in hasNonEmptyLocation()
345 if (Entry.getInstr()->isDebugEntryValue()) in clobberRegEntries()
347 if (Entry.getInstr()->hasDebugOperandForReg(RegNo)) { in clobberRegEntries()
350 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
354 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp154 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
155 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
188 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
211 MachineInstr *MI = SU->getInstr(); in getAluKind()
285 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
314 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
316 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
380 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
429 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
H A DAMDGPUIGroupLP.cpp203 << *SU.getInstr()); in add()
380 return SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER; in reset()
438 if (SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) in makePipeline()
929 if (TII->isMFMAorWMMA(*I->getInstr())) in apply()
963 if (FoundTrans && TII->isMFMAorWMMA(*I->getInstr())) { in apply()
970 if (!FoundTrans && TII->isTRANS(I->getInstr()->getOpcode())) in apply()
997 if (!SU || !TII->isMFMAorWMMA(*ChainSeed->getInstr())) in apply()
1007 if (TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr())) { in apply()
1118 auto Opc = SU->getInstr()->getOpcode(); in apply()
1131 return SU->getInstr()->getOpcode() == AMDGPU::V_FMA_F32_e64 || in apply()
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H A DGCNDPPCombine.cpp253 if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) { in createDPPInst()
299 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
332 if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) { in createDPPInst()
352 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
353 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
432 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
435 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
436 return DPPInst.getInstr(); in createDPPInst()
626 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
H A DSIMachineScheduler.cpp250 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
313 RPTracker.setPos(SU->getInstr()); in initRegPressure()
394 TopRPTracker.setPos(SU->getInstr()); in schedule()
1106 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1118 if (!SIInstrInfo::isEXP(*SuccSU->getInstr())) { in colorExports()
1304 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1333 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1773 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1783 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1804 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
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H A DAMDGPUExportClustering.cpp29 return SIInstrInfo::isEXP(*SU.getInstr()); in isExport()
33 const MachineInstr *MI = SU->getInstr(); in isPositionExport()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp105 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
106 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
187 if (DAG->ExitSU.getInstr()) in apply()
195 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
214 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
H A DVLIWMachineScheduler.cpp109 if (!SU || !SU->getInstr()) in isResourceAvailable()
114 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
116 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
162 switch (SU->getInstr()->getOpcode()) { in reserveResources()
164 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
186 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
323 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
362 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
429 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
529 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta, in readyQueueVerboseDump()
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H A DMachinePipeliner.cpp856 OrderedInsts.push_back(SU->getInstr()); in schedule()
857 Cycles[SU->getInstr()] = Cycle; in schedule()
858 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
979 const MachineInstr *MI = SU->getInstr(); in getUnderlyingObjects()
1007 MachineInstr &SrcMI = *Src.SU->getInstr(); in hasLoopCarriedMemDep()
1008 MachineInstr &DstMI = *Dst.SU->getInstr(); in hasLoopCarriedMemDep()
1061 const MachineInstr *MI = SU->getInstr(); in append()
1089 MachineInstr *MI = SU->getInstr(); in getInstrTag()
1197 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
1252 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
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H A DScheduleDAGInstrs.cpp260 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
269 const MCInstrDesc &DefMIDesc = SU->getInstr()->getDesc(); in addPhysRegDataDeps()
292 UseInstr = UseSU->getInstr(); in addPhysRegDataDeps()
301 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
316 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
338 MachineInstr *DefInstr = DefSU->getInstr(); in addPhysRegDeps()
426 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
474 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
521 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addVRegDefDeps()
546 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
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H A DSlotIndexes.cpp137 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
150 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
221 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
270 if (ILE.getInstr()) in print()
271 OS << *ILE.getInstr(); in print()
H A DMachineScheduler.cpp1111 MachineInstr *MI = SU->getInstr(); in schedule()
1434 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1631 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); in updatePressureDiffs()
1660 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in updatePressureDiffs()
1668 << ") " << *SU->getInstr(); in updatePressureDiffs()
1680 if (EntrySU.getInstr() != nullptr) in dump()
1689 if (SchedModel.mustBeginGroup(SU.getInstr()) && in dump()
1690 SchedModel.mustEndGroup(SU.getInstr())) in dump()
1696 if (ExitSU.getInstr() != nullptr) in dump()
1862 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in computeCyclicCriticalPath()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp372 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVI()
392 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::MOVQ), SReg).addImm(~Imm & 0xFF); in ExpandMOVI()
393 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::NOT8d), SubReg).addReg(SubReg); in ExpandMOVI()
404 BuildMI(MBB, MIB.getInstr(), DL, get(M68k::SUB32ar), SReg) in ExpandMOVI()
459 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n'); in ExpandMOVX_RR()
462 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n"); in ExpandMOVX_RR()
474 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVSZX_RR()
506 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc); in ExpandMOVSZX_RR()
511 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
514 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
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/freebsd/contrib/llvm-project/llvm/include/llvm/SandboxIR/
H A DBasicBlock.h36 LLVM_ABI pointer getInstr(llvm::BasicBlock::iterator It) const;
42 reference operator*() const { return *getInstr(It); }
62 pointer get() const { return getInstr(It); } in get()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorMaskDAGMutation.cpp58 return isCopyToV0(*DepSU.getInstr()); in isSoleUseCopyToV0()
71 const MachineInstr *MI = SU.getInstr(); in apply()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp532 const MachineInstr *SrcMI = ISU.getInstr(); in makeBundleAssumptions()
534 const MachineInstr *DstMI = DepSU.getInstr(); in makeBundleAssumptions()
557 auto &SrcInst = *ISU.getInstr(); in memoryRAWHazard()
558 auto &DstInst = *Dep.getSUnit()->getInstr(); in memoryRAWHazard()
608 const MachineInstr *SrcMI = ISU.getInstr(); in modifyBypasses()
634 const MachineInstr *DstMI = DepSU.getInstr(); in modifyBypasses()
858 const MachineInstr *SrcMI = ISU.getInstr(); in modifyBypasses()
884 const MachineInstr *DstMI = DepSU.getInstr(); in modifyBypasses()
933 MachineInstr *SrcMI = SU.getInstr(); in modifyBypasses()
943 MachineInstr *DstMI = DepSU.getInstr(); in modifyBypasses()
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H A DARMHazardRecognizer.cpp45 MachineInstr *MI = SU->getInstr(); in getHazardType()
88 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
183 MachineInstr &L0 = *SU->getInstr(); in getHazardType()
255 MachineInstr &MI = *SU->getInstr(); in EmitInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp66 MachineInstr *Instr0 = TryCand.SU->getInstr(); in tryCandidate()
67 MachineInstr *Instr1 = Cand.SU->getInstr(); in tryCandidate()

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