Lines Matching refs:getInstr
204 << *SU.getInstr()); in add()
245 assert(SU.getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER || in resetEdges()
246 SU.getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER || in resetEdges()
247 SU.getInstr()->getOpcode() == AMDGPU::IGLP_OPT); in resetEdges()
398 return SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER; in reset()
456 if (SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) in makePipeline()
951 if (TII->isMFMAorWMMA(*I->getInstr())) in apply()
988 if (FoundTrans && TII->isMFMAorWMMA(*I->getInstr())) { in apply()
995 if (!FoundTrans && TII->isTRANS(I->getInstr()->getOpcode())) in apply()
1022 if (!SU || !TII->isMFMAorWMMA(*ChainSeed->getInstr())) in apply()
1032 if (TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr())) { in apply()
1145 auto Opc = SU->getInstr()->getOpcode(); in apply()
1158 return SU->getInstr()->getOpcode() == AMDGPU::V_FMA_F32_e64 || in apply()
1159 SU->getInstr()->getOpcode() == AMDGPU::V_PK_FMA_F32; in apply()
1170 return SU->getInstr()->getOpcode() == AMDGPU::V_ADD_F32_e32; in apply()
1275 if (!SU || !TII->isMFMAorWMMA(*ChainSeed->getInstr())) in apply()
1285 if (TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr())) { in apply()
1322 if (TII->isTRANS(SU.getInstr()->getOpcode())) { in apply()
1383 auto Opc = SU.getInstr()->getOpcode(); in analyzeDAG()
1395 if (TII->isMFMAorWMMA(*SU.getInstr())) in analyzeDAG()
1436 return isCvt(Succ.getSUnit()->getInstr()->getOpcode()); in analyzeDAG()
1485 return TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr()); in analyzeDAG()
1496 if (TII->isDS(Pred.getSUnit()->getInstr()->getOpcode()) && in analyzeDAG()
1497 Pred.getSUnit()->getInstr()->mayLoad()) in analyzeDAG()
1513 auto Opc = Pred.getSUnit()->getInstr()->getOpcode(); in analyzeDAG()
1520 auto Opc = Pred.getSUnit()->getInstr()->getOpcode(); in analyzeDAG()
1533 return TII->isMFMAorWMMA(*Succ.getSUnit()->getInstr()); in analyzeDAG()
1866 if (TII->isMFMAorWMMA(*Elt.getInstr())) { in apply()
1894 auto MI = SU->getInstr(); in apply()
1903 if (TII->isDS(*SuccUnit->getInstr()) && in apply()
1904 SuccUnit->getInstr()->mayStore()) { in apply()
1964 auto MI = SU->getInstr(); in apply()
1975 auto Op = Elt->getInstr()->getOperand(0); in apply()
2024 if (Pred.getSUnit()->getInstr()->getOpcode() == in apply()
2082 auto I = SU.getInstr(); in applyIGLPStrategy()
2091 if (Pred.getSUnit()->getInstr()->getOpcode() == in applyIGLPStrategy()
2118 if (Pred.getSUnit()->getInstr()->getOpcode() != AMDGPU::V_PERM_B32_e64) in applyIGLPStrategy()
2125 auto MI = Succ.getSUnit()->getInstr(); in applyIGLPStrategy()
2453 if (A == B || A->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) in link()
2476 if (A->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) in link()
2502 MachineInstr &MI = *SU.getInstr(); in canAddSU()
2570 unsigned Opc = R->getInstr()->getOpcode(); in apply()
2597 MachineInstr &MI = *SchedBarrier.getInstr(); in addSchedBarrierEdges()
2660 MachineInstr &SGB = *RIter->getInstr(); in initSchedGroupBarrierPipelineStage()
2674 (IGLPStrategyID)SU.getInstr()->getOperand(0).getImm(); in initIGLPOpt()