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Searched refs:getImm (Results 1 – 25 of 460) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp80 .getImm(); in getCFAluSize()
87 .getImm(); in isCFAluEnabled()
128 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
130 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
132 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
133 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
144 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
145 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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H A DGCNDPPCombine.cpp228 RowMaskOpnd->getImm() == 0xF && BankMaskOpnd->getImm() == 0xF; in createDPPInst()
283 (0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst()
284 DPPInst.addImm(Mod0->getImm()); in createDPPInst()
307 (0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst()
308 DPPInst.addImm(Mod1->getImm()); in createDPPInst()
340 (0LL == (Mod2->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst()
341 DPPInst.addImm(Mod2->getImm()); in createDPPInst()
359 DPPInst.addImm(ClampOpr->getImm()); in createDPPInst()
368 DPPInst.addImm(OmodOpr->getImm()); in createDPPInst()
374 OpSel |= (Mod0 ? (!!(Mod0->getImm() & SISrcMods::OP_SEL_0) << 0) : 0); in createDPPInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp58 int32_t TruncatedImm = static_cast<int32_t>(MO.getImm()); in printOperand()
79 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
85 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
88 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
96 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
101 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
123 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
128 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
130 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetStreamer.h33 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
34 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
39 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
40 return A.getOperand(1).getImm() < B.getOperand(1).getImm(); in operator()
43 if (A.getOperand(4).getImm() != B.getOperand(4).getImm()) in operator()
44 return A.getOperand(4).getImm() < B.getOperand(4).getImm(); in operator()
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H A DSystemZAsmPrinter.cpp44 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
49 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
58 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
63 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
73 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
74 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
75 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
125 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
135 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
217 .addImm(MI->getOperand(0).getImm()) in emitInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp134 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
145 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
156 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
165 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
172 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); in printInst()
195 MI->getOperand(3).getImm() == -4) { in printInst()
224 MI->getOperand(4).getImm() == 4) { in printInst()
319 switch (MI->getOperand(0).getImm()) { in printInst()
348 markup(O, Markup::Immediate) << '#' << formatImm(Op.getImm()); in printOperand()
388 Address, Op.getImm()); in printOperand()
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H A DARMMCCodeEmitter.cpp236 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
331 return MO.getImm(); in getModImmOpValue()
348 unsigned SoImm = MO.getImm(); in getT2SOImmOpValue()
379 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue()
568 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
589 int32_t SImm = MO1.getImm();
617 if (MO.isImm()) return MO.getImm(); in EncodeAddrModeOpValues()
655 return encodeThumbBLOffset(MO.getImm()); in encodeThumbBLOffset()
668 return encodeThumbBLOffset(MO.getImm());
680 return (MO.getImm() >> in getThumbBLXTargetOpValue()
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H A DARMMCTargetDesc.cpp41 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
42 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
45 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
46 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
47 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
54 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
61 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
62 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
68 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || in getMCRDeprecationInfo()
69 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { in getMCRDeprecationInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp63 O << MC.getImm(); in printOperand()
97 int64_t Val = MC.getImm() + 4; in printBranchTarget()
112 int64_t Val = MC.getImm() + 4; in printJumpTarget()
128 int64_t Val = MC.getImm() + 4; in printCallOperand()
143 int64_t Value = MI->getOperand(OpNum).getImm(); in printL32RTarget()
160 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm8_AsmOperand()
172 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm8_sh8_AsmOperand()
184 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm12_AsmOperand()
195 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm12m_AsmOperand()
206 int64_t Value = MI->getOperand(OpNum).getImm(); in printUimm4_AsmOperand()
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H A DXtensaMCCodeEmitter.cpp152 uint32_t Res = static_cast<uint32_t>(MO.getImm()); in getMachineOpValue()
167 return MO.getImm(); in getJumpTargetEncoding()
180 return static_cast<uint32_t>(MO.getImm()); in getBranchTargetEncoding()
204 int32_t Res = MO.getImm(); in getCallEncoding()
225 int32_t Res = MO.getImm(); in getL32RTargetEncoding()
245 uint32_t Res = static_cast<uint32_t>(MI.getOperand(OpNo + 1).getImm()); in getMemRegEncoding()
277 int32_t Res = MO.getImm(); in getImm8OpValue()
289 int32_t Res = MO.getImm(); in getImm8_sh8OpValue()
302 int32_t Res = MO.getImm(); in getImm12OpValue()
314 uint32_t Res = static_cast<uint32_t>(MO.getImm()); in getUimm4OpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp116 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
139 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
146 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
196 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
205 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
206 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
208 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
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H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
156 OS << formatHex(Op.getImm()); in printOperand()
167 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
181 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
193 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.cpp115 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
116 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
117 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
139 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
140 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
165 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
189 unsigned char L = MI->getOperand(0).getImm(); in printInst()
222 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
319 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
329 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp247 int64_t getImm() const { in getImm() function
350 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } in isU1Imm()
351 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } in isU2Imm()
352 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } in isU3Imm()
353 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } in isU4Imm()
354 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } in isU5Imm()
355 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } in isS5Imm()
356 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } in isU6Imm()
358 isUInt<6>(getImm()) && in isU6ImmX2()
359 (getImm() & 1) == 0; } in isU6ImmX2()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp230 return static_cast<unsigned>(MO.getImm()); in getLdStUImm12OpValue()
241 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
262 return MO.getImm(); in getAdrLabelOpValue()
287 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
289 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
293 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
324 return MO.getImm(); in getCondBranchTargetOpValue()
347 return -(MO.getImm()); in getLoadLiteralOpValue()
369 return MO.getImm(); in getMoveWideImmOpValue()
385 unsigned SignExtend = MI.getOperand(OpIdx).getImm(); in getTestBranchTargetOpValue()
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H A DAArch64InstPrinter.cpp110 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
113 switch (Op3.getImm()) { in printInst()
151 int64_t immr = Op2.getImm(); in printInst()
152 int64_t imms = Op3.getImm(); in printInst()
186 if (Op2.getImm() > Op3.getImm()) { in printInst()
192 markup(O, Markup::Immediate) << "#" << (Is64Bit ? 64 : 32) - Op2.getImm(); in printInst()
194 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1; in printInst()
205 markup(O, Markup::Immediate) << "#" << Op2.getImm(); in printInst()
207 markup(O, Markup::Immediate) << "#" << Op3.getImm() in printInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600InstPrinter.cpp35 int BankSwizzle = MI->getOperand(OpNo).getImm(); in printBankSwizzle()
63 unsigned CT = MI->getOperand(OpNo).getImm(); in printCT()
78 int KCacheMode = MI->getOperand(OpNo).getImm(); in printKCache()
80 int KCacheBank = MI->getOperand(OpNo - 2).getImm(); in printKCache()
82 int KCacheAddr = MI->getOperand(OpNo + 2).getImm(); in printKCache()
98 int64_t Imm = Op.getImm(); in printLiteral()
113 switch (MI->getOperand(OpNo).getImm()) { in printOMOD()
154 O << Op.getImm(); in printOperand()
177 unsigned Sel = MI->getOperand(OpNo).getImm(); in printRSel()
218 if (Op.getImm() == 0) { in printWrite()
H A DR600MCCodeEmitter.cpp100 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset in encodeInstruction()
109 int64_t Sampler = MI.getOperand(14).getImm(); in encodeInstruction()
112 MI.getOperand(2).getImm(), MI.getOperand(3).getImm(), in encodeInstruction()
113 MI.getOperand(4).getImm(), MI.getOperand(5).getImm()}; in encodeInstruction()
114 int64_t Offsets[3] = {MI.getOperand(6).getImm() & 0x1F, in encodeInstruction()
115 MI.getOperand(7).getImm() & 0x1F, in encodeInstruction()
116 MI.getOperand(8).getImm() & 0x1F}; in encodeInstruction()
175 return MO.getImm(); in getMachineOpValue()
H A DAMDGPUInstPrinter.cpp53 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
67 int64_t Imm = Op.getImm(); in printU16ImmOperand()
76 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
81 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
86 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
92 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
97 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
105 uint32_t Imm = MI->getOperand(OpNo).getImm(); in printOffset()
122 uint32_t Imm = MI->getOperand(OpNo).getImm(); in printFlatOffset()
141 if (MI->getOperand(OpNo).getImm()) { in printOffset0()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DStackMaps.h47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID()
51 return MI->getOperand(NBytesPos).getImm(); in getNumPatchBytes()
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID()
105 return getMetaOper(NBytesPos).getImm(); in getNumPatchBytes()
115 return getMetaOper(CCPos).getImm(); in getCallingConv()
122 return MI->getOperand(getMetaIdx(NArgPos)).getImm(); in getNumCallArgs()
189 return MI->getOperand(NumDefs + NCallArgsPos).getImm() + MetaEnd + NumDefs; in getVarIdx()
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID()
208 return MI->getOperand(NumDefs + NBytesPos).getImm(); in getNumPatchBytes()
218 return MI->getOperand(getCCIdx()).getImm(); in getCallingConv()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp159 const MCExpr *getImm() const { in getImm() function
407 addExpr(Inst, getImm()); in addImmOperands()
412 addExpr(Inst, getImm()); in addBrTargetOperands()
417 addExpr(Inst, getImm()); in addCallTargetOperands()
422 addExpr(Inst, getImm()); in addCondCodeOperands()
456 addExpr(Inst, getImm()); in addImmShiftOperands()
461 addExpr(Inst, getImm()); in addImm10Operands()
466 if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(getImm())) in addLoImm16Operands()
469 else if (isa<LanaiMCExpr>(getImm())) { in addLoImm16Operands()
471 const LanaiMCExpr *SymbolRefExpr = dyn_cast<LanaiMCExpr>(getImm()); in addLoImm16Operands()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp35 return MO.getImm() - 1; in getOImmOpValue()
45 auto V = (MO.getImm() <= 3) ? 4 : MO.getImm(); in getImmOpValueIDLY()
57 return MSB.getImm() - LSB.getImm(); in getImmOpValueMSBSize()
133 .addImm(MI.getOperand(2).getImm() + 1); in expandRSUBI()
209 .addImm(MI.getOperand(2).getImm() + 1); in encodeInstruction()
215 .addImm(MI.getOperand(2).getImm() + 1); in encodeInstruction()
221 .addImm(32 - MI.getOperand(2).getImm()); in encodeInstruction()
224 auto V = 1 << MI.getOperand(1).getImm(); in encodeInstruction()
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H A DCSKYInstPrinter.cpp136 O << formatHex(MO.getImm()); in printOperand()
138 O << MO.getImm(); in printOperand()
153 O << MO.getImm(); in printDataSymbol()
166 uint64_t Target = Address + MO.getImm(); in printConstpool()
170 O << MO.getImm(); in printConstpool()
192 uint64_t Target = Address + MO.getImm(); in printCSKYSymbolOperand()
196 O << MO.getImm(); in printCSKYSymbolOperand()
202 auto V = MI->getOperand(OpNo).getImm(); in printPSRFlag()
227 auto V = MI->getOperand(OpNum).getImm(); in printRegisterList()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp105 encodeSLEB128(int32_t(MO.getImm()), OS); in encodeInstruction()
108 encodeULEB128(uint32_t(MO.getImm()), OS); in encodeInstruction()
111 encodeSLEB128(int64_t(MO.getImm()), OS); in encodeInstruction()
115 support::endian::write<uint8_t>(OS, MO.getImm(), in encodeInstruction()
119 support::endian::write<uint16_t>(OS, MO.getImm(), in encodeInstruction()
123 support::endian::write<uint32_t>(OS, MO.getImm(), in encodeInstruction()
127 support::endian::write<uint64_t>(OS, MO.getImm(), in encodeInstruction()
136 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
139 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp94 markup(O, Markup::Immediate) << formatImm(MO.getImm()); in printOperand()
111 uint64_t Target = Address + MO.getImm(); in printBranchOperand()
116 markup(O, Markup::Target) << formatImm(MO.getImm()); in printBranchOperand()
123 unsigned Imm = MI->getOperand(OpNo).getImm(); in printCSRSystemRegister()
137 unsigned FenceArg = MI->getOperand(OpNo).getImm(); in printFenceArg()
155 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm()); in printFRMArg()
165 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm()); in printFRMArgLegacy()
177 unsigned Imm = MI->getOperand(OpNo).getImm(); in printFPImmOperand()
210 unsigned Imm = MI->getOperand(OpNo).getImm(); in printVTypeI()
227 unsigned Imm = MI->getOperand(OpNo).getImm(); in printRlist()
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