| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ClauseMergePass.cpp | 80 .getImm(); in getCFAluSize()
87 .getImm(); in isCFAluEnabled()
128 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
130 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
132 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
133 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
144 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
145 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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| H A D | GCNDPPCombine.cpp | 234 RowMaskOpnd->getImm() == 0xF && BankMaskOpnd->getImm() == 0xF; in createDPPInst()
289 (0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst()
290 DPPInst.addImm(Mod0->getImm()); in createDPPInst()
313 (0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst()
314 DPPInst.addImm(Mod1->getImm()); in createDPPInst()
346 (0LL == (Mod2->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)))); in createDPPInst()
347 DPPInst.addImm(Mod2->getImm()); in createDPPInst()
365 DPPInst.addImm(ClampOpr->getImm()); in createDPPInst()
374 DPPInst.addImm(OmodOpr->getImm()); in createDPPInst()
380 OpSel |= (Mod0 ? (!!(Mod0->getImm() & SISrcMods::OP_SEL_0) << 0) : 0); in createDPPInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/ |
| H A D | VEInstPrinter.cpp | 59 int32_t TruncatedImm = static_cast<int32_t>(MO.getImm()); in printOperand()
72 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
78 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
79 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
81 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
89 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
94 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
108 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
113 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
115 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 132 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
143 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
154 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
163 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
170 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())); in printInst()
193 MI->getOperand(3).getImm() == -4) { in printInst()
222 MI->getOperand(4).getImm() == 4) { in printInst()
317 switch (MI->getOperand(0).getImm()) { in printInst()
346 markup(O, Markup::Immediate) << '#' << formatImm(Op.getImm()); in printOperand()
386 Address, Op.getImm()); in printOperand()
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| H A D | ARMMCCodeEmitter.cpp | 234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
348 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue()
575 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
596 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
624 if (MO.isImm()) return MO.getImm(); in getBranchTargetOpValue()
662 return encodeThumbBLOffset(MO.getImm()); in getThumbBLTargetOpValue()
675 return encodeThumbBLOffset(MO.getImm()); in getThumbBLXTargetOpValue()
687 return (MO.getImm() >> 1); in getThumbBRTargetOpValue()
699 return (MO.getImm() >> 1); in getThumbBCCTargetOpValue()
710 return (MO.getImm() >> 1); in getThumbCBTargetOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/ |
| H A D | XtensaInstPrinter.cpp | 54 O << MC.getImm(); in printOperand()
88 int64_t Val = MC.getImm() + 4; in printBranchTarget()
100 int64_t Val = MC.getImm() + 4; in printLoopTarget()
112 int64_t Val = MC.getImm() + 4; in printJumpTarget()
125 int64_t Val = MC.getImm() + 4; in printCallOperand()
147 int64_t Value = MI->getOperand(OpNum).getImm(); in printL32RTarget()
184 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm8_AsmOperand()
196 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm8_sh8_AsmOperand()
208 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm12_AsmOperand()
219 int64_t Value = MI->getOperand(OpNum).getImm(); in printImm12m_AsmOperand()
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| H A D | XtensaMCCodeEmitter.cpp | 196 uint32_t Res = static_cast<uint32_t>(MO.getImm()); in getMachineOpValue()
211 return MO.getImm(); in getJumpTargetEncoding()
223 return static_cast<uint32_t>(MO.getImm()); in getBranchTargetEncoding()
249 return static_cast<uint32_t>(MO.getImm()); in getLoopTargetEncoding()
265 int32_t Res = MO.getImm(); in getCallEncoding()
285 int32_t Res = MO.getImm(); in getL32RTargetEncoding()
304 uint32_t Res = static_cast<uint32_t>(MI.getOperand(OpNo + 1).getImm()); in getMemRegEncoding()
351 int32_t Res = MO.getImm(); in getImm8OpValue()
363 int32_t Res = MO.getImm(); in getImm8_sh8OpValue()
376 int32_t Res = MO.getImm(); in getImm12OpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiInstPrinter.cpp | 46 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
48 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
49 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
53 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
58 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
63 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
152 OS << formatHex(Op.getImm()); in printOperand()
163 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
177 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
189 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
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| H A D | LanaiMCCodeEmitter.cpp | 114 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
137 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
144 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
152 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
194 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
199 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
202 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
203 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
204 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
206 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 249 int64_t getImm() const { in getImm() function
352 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } in isU1Imm()
353 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } in isU2Imm()
354 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } in isU3Imm()
355 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } in isU4Imm()
356 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } in isU5Imm()
357 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } in isS5Imm()
358 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } in isU6Imm()
360 isUInt<6>(getImm()) && in isU6ImmX2()
361 (getImm() & 1) == 0; } in isU6ImmX2()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZTargetStreamer.h | 38 A.getNumOperands() == 5 && A.getOperand(2).getImm() == 1 && in operator()
39 B.getOperand(2).getImm() == 1 && "Unexpected EXRL target MCInst"); in operator()
44 if (A.getOperand(1).getImm() != B.getOperand(1).getImm()) in operator()
45 return A.getOperand(1).getImm() < B.getOperand(1).getImm(); in operator()
48 if (A.getOperand(4).getImm() != B.getOperand(4).getImm()) in operator()
49 return A.getOperand(4).getImm() < B.getOperand(4).getImm(); in operator()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCInstPrinter.cpp | 116 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
117 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
118 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
140 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
141 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
166 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
190 unsigned char L = MI->getOperand(0).getImm(); in printInst()
222 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
319 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
329 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 241 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
252 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
273 return MO.getImm(); in getAdrLabelOpValue()
295 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
297 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
301 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
331 return MO.getImm(); in getCondBranchTargetOpValue()
349 return MO.getImm(); in getCondCompBranchTargetOpValue()
369 return -(MO.getImm()); in getPAuthPCRelOpValue()
388 return MO.getImm(); in getLoadLiteralOpValue()
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| H A D | AArch64InstPrinter.cpp | 109 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
112 switch (Op3.getImm()) { in printInst()
150 int64_t immr = Op2.getImm(); in printInst()
151 int64_t imms = Op3.getImm(); in printInst()
185 if (Op2.getImm() > Op3.getImm()) { in printInst()
191 markup(O, Markup::Immediate) << "#" << (Is64Bit ? 64 : 32) - Op2.getImm(); in printInst()
193 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1; in printInst()
204 markup(O, Markup::Immediate) << "#" << Op2.getImm(); in printInst()
206 markup(O, Markup::Immediate) << "#" << Op3.getImm() - Op2.getImm() + 1; in printInst()
214 int ImmR = MI->getOperand(3).getImm(); in printInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | R600InstPrinter.cpp | 35 int BankSwizzle = MI->getOperand(OpNo).getImm(); in printBankSwizzle()
63 unsigned CT = MI->getOperand(OpNo).getImm(); in printCT()
78 int KCacheMode = MI->getOperand(OpNo).getImm(); in printKCache()
80 int KCacheBank = MI->getOperand(OpNo - 2).getImm(); in printKCache()
82 int KCacheAddr = MI->getOperand(OpNo + 2).getImm(); in printKCache()
98 int64_t Imm = Op.getImm(); in printLiteral()
114 switch (MI->getOperand(OpNo).getImm()) { in printOMOD()
155 O << Op.getImm(); in printOperand()
178 unsigned Sel = MI->getOperand(OpNo).getImm(); in printRSel()
219 if (Op.getImm() == 0) { in printWrite()
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| H A D | R600MCCodeEmitter.cpp | 99 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset in encodeInstruction()
108 int64_t Sampler = MI.getOperand(14).getImm(); in encodeInstruction()
111 MI.getOperand(2).getImm(), MI.getOperand(3).getImm(), in encodeInstruction()
112 MI.getOperand(4).getImm(), MI.getOperand(5).getImm()}; in encodeInstruction()
113 int64_t Offsets[3] = {MI.getOperand(6).getImm() & 0x1F, in encodeInstruction()
114 MI.getOperand(7).getImm() & 0x1F, in encodeInstruction()
115 MI.getOperand(8).getImm() & 0x1F}; in encodeInstruction()
174 return MO.getImm(); in getMachineOpValue()
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| H A D | AMDGPUInstPrinter.cpp | 61 int64_t Imm = Op.getImm(); in printU16ImmOperand()
70 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
76 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
84 uint64_t Imm = MI->getOperand(OpNo).getImm(); in printFP64ImmOperand()
93 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
101 uint32_t Imm = MI->getOperand(OpNo).getImm(); in printOffset()
118 uint32_t Imm = MI->getOperand(OpNo).getImm(); in printFlatOffset()
143 O << formatHex(MI->getOperand(OpNo).getImm()); in printSMEMOffset()
154 auto Imm = MI->getOperand(OpNo).getImm(); in printCPol()
259 unsigned Dim = MI->getOperand(OpNo).getImm(); in printDim()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 158 const MCExpr *getImm() const { in getImm() function
406 addExpr(Inst, getImm()); in addImmOperands()
411 addExpr(Inst, getImm()); in addBrTargetOperands()
416 addExpr(Inst, getImm()); in addCallTargetOperands()
421 addExpr(Inst, getImm()); in addCondCodeOperands()
455 addExpr(Inst, getImm()); in addImmShiftOperands()
460 addExpr(Inst, getImm()); in addImm10Operands()
465 if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(getImm())) in addLoImm16Operands()
468 else if (isa<MCSpecifierExpr>(getImm())) { in addLoImm16Operands()
470 const auto *SymbolRefExpr = dyn_cast<MCSpecifierExpr>(getImm()); in addLoImm16Operands()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | StackMaps.h | 48 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID()
52 return MI->getOperand(NBytesPos).getImm(); in getNumPatchBytes()
102 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID()
106 return getMetaOper(NBytesPos).getImm(); in getNumPatchBytes()
116 return getMetaOper(CCPos).getImm(); in getCallingConv()
123 return MI->getOperand(getMetaIdx(NArgPos)).getImm(); in getNumCallArgs()
190 return MI->getOperand(NumDefs + NCallArgsPos).getImm() + MetaEnd + NumDefs; in getVarIdx()
205 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID()
209 return MI->getOperand(NumDefs + NBytesPos).getImm(); in getNumPatchBytes()
219 return MI->getOperand(getCCIdx()).getImm(); in getCallingConv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 47 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
52 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
61 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
76 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
77 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
78 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
126 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
136 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
237 .addImm(MI->getOperand(0).getImm()) in emitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVInstPrinter.cpp | 99 markup(O, Markup::Immediate) << formatImm(MO.getImm()); in printOperand()
116 uint64_t Target = Address + MO.getImm(); in printBranchOperand()
121 markup(O, Markup::Target) << formatImm(MO.getImm()); in printBranchOperand()
128 unsigned Imm = MI->getOperand(OpNo).getImm(); in printCSRSystemRegister()
144 unsigned FenceArg = MI->getOperand(OpNo).getImm(); in printFenceArg()
162 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm()); in printFRMArg()
172 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm()); in printFRMArgLegacy()
184 unsigned Imm = MI->getOperand(OpNo).getImm(); in printFPImmOperand()
217 unsigned Imm = MI->getOperand(OpNo).getImm(); in printVTypeI()
232 unsigned Imm = MI->getOperand(OpNo).getImm(); in printXSfmmVType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyMCCodeEmitter.cpp | 104 encodeSLEB128(int32_t(MO.getImm()), OS); in encodeInstruction()
107 encodeULEB128(uint32_t(MO.getImm()), OS); in encodeInstruction()
110 encodeSLEB128(int64_t(MO.getImm()), OS); in encodeInstruction()
114 support::endian::write<uint8_t>(OS, MO.getImm(), in encodeInstruction()
118 support::endian::write<uint16_t>(OS, MO.getImm(), in encodeInstruction()
122 support::endian::write<uint32_t>(OS, MO.getImm(), in encodeInstruction()
126 support::endian::write<uint64_t>(OS, MO.getImm(), in encodeInstruction()
135 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
143 encodeULEB128(uint32_t(MO.getImm()), OS); in encodeInstruction()
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| H A D | WebAssemblyInstPrinter.cpp | 70 assert(MI->getOperand(TableOperand).getImm() == 0); in printInst()
91 NumVariadicDefs = MI->getOperand(0).getImm(); in printInst()
114 uint64_t Depth = Op.getImm(); in printInst()
157 unsigned NumCatches = Op.getImm(); in printInst()
159 int64_t CatchOpcode = MI->getOperand(OpIdx++).getImm(); in printInst()
253 uint64_t Depth = MI->getOperand(0).getImm(); in printInst()
333 O << Op.getImm(); in printOperand()
359 O << MI->getOperand(I).getImm(); in printBrList()
367 int64_t Imm = MI->getOperand(OpNo).getImm(); in printWebAssemblyP2AlignOperand()
378 auto Imm = static_cast<unsigned>(Op.getImm()); in printWebAssemblySignatureOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 641 const int64_t Type = MI.getOperand(1).getImm(); in LowerKCFI_CHECK()
699 uint32_t AccessInfo = MI.getOperand(1).getImm(); in LowerHWASAN_CHECK_MEMACCESS()
704 uint64_t FixedShadowOffset = IsFixedShadow ? MI.getOperand(2).getImm() : 0; in LowerHWASAN_CHECK_MEMACCESS()
1090 O << MO.getImm(); in printOperand()
1162 if (MO.isImm() && MO.getImm() == 0) { in PrintAsmOperand()
1701 int64_t CallTarget = Opers.getCallTarget().getImm(); in LowerPATCHPOINT()
1743 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm()); in LowerSTATEPOINT()
1771 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm()); in LowerFAULTING_OP()
1773 unsigned Opcode = FaultingMI.getOperand(3).getImm(); in LowerFAULTING_OP()
2182 auto Key = (AArch64PACKey::ID)MI->getOperand(1).getImm(); in emitPtrauthBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/ |
| H A D | CSKYInstPrinter.cpp | 134 O << formatHex(MO.getImm()); in printOperand()
136 O << MO.getImm(); in printOperand()
151 O << MO.getImm(); in printDataSymbol()
164 uint64_t Target = Address + MO.getImm(); in printConstpool()
168 O << MO.getImm(); in printConstpool()
190 uint64_t Target = Address + MO.getImm(); in printCSKYSymbolOperand()
194 O << MO.getImm(); in printCSKYSymbolOperand()
200 auto V = MI->getOperand(OpNo).getImm(); in printPSRFlag()
225 auto V = MI->getOperand(OpNum).getImm(); in printRegisterList()
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