| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/ |
| H A D | MachineValueType.h | 143 return (isFixedLengthVector() && getFixedSizeInBits() == 16); in is16BitVector()
148 return (isFixedLengthVector() && getFixedSizeInBits() == 32); in is32BitVector()
153 return (isFixedLengthVector() && getFixedSizeInBits() == 64); in is64BitVector()
158 return (isFixedLengthVector() && getFixedSizeInBits() == 128); in is128BitVector()
163 return (isFixedLengthVector() && getFixedSizeInBits() == 256); in is256BitVector()
168 return (isFixedLengthVector() && getFixedSizeInBits() == 512); in is512BitVector()
173 return (isFixedLengthVector() && getFixedSizeInBits() == 1024); in is1024BitVector()
178 return (isFixedLengthVector() && getFixedSizeInBits() == 2048); in is2048BitVector()
344 uint64_t getFixedSizeInBits() const { in getFixedSizeInBits() function
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TypePromotion.cpp | 949 if (RegisterBitWidth < PromotedVT.getFixedSizeInBits()) { in run()
956 return PromotedVT.getFixedSizeInBits(); in run()
977 auto PromoteWidth = ZExtVT.getFixedSizeInBits(); in run()
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| H A D | TargetLoweringBase.cpp | 770 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions()
1499 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() && in computeRegisterProperties()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 297 uint64_t ValSize = VA.getValVT().getFixedSizeInBits(); in assignValueToReg()
298 uint64_t LocSize = VA.getLocVT().getFixedSizeInBits(); in assignValueToReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Subtarget.h | 433 return VT.getFixedSizeInBits() > AArch64::SVEBitsPerBlock || in useSVEForFixedLengthVectors()
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| H A D | AArch64ISelLowering.cpp | 2153 if (OpVT.getFixedSizeInBits() > 64) in shouldExpandGetActiveLaneMask()
4545 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
4546 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
4862 uint64_t VTSize = VT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
4863 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorINT_TO_FP()
5747 unsigned Op2BitWidth = Op2VT.getFixedSizeInBits(); in LowerVectorMatch()
7061 unsigned int NewShiftNo = ShiftNo->getZExtValue() % VT.getFixedSizeInBits(); in LowerFunnelShift()
7067 NewShiftNo = VT.getFixedSizeInBits() - NewShiftNo; in LowerFunnelShift()
7600 if (VT.getFixedSizeInBits() <= 128) in useSVEForFixedLengthVectorVT()
7608 if (VT.getFixedSizeInBits() > Subtarget->getMinSVEVectorSizeInBits()) in useSVEForFixedLengthVectorVT()
[all …]
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| H A D | AArch64ISelLowering.h | 384 return VT.getFixedSizeInBits() >= 64; // vector 'bic' in hasAndNot()
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| H A D | AArch64ISelDAGToDAG.cpp | 285 /* High */ EltVT.getFixedSizeInBits(), in SelectSVEShiftSplatImmR()
4237 .trunc(VT.getFixedSizeInBits()) in SelectSVEAddSubImm()
4278 .trunc(VT.getFixedSizeInBits()) in SelectSVEAddSubSSatImm()
4327 .trunc(VT.getFixedSizeInBits()) in SelectSVECpyDupImm()
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| H A D | AArch64TargetTransformInfo.cpp | 3690 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits()) in getExtractWithExtendCost()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 376 uint64_t getFixedSizeInBits() const { in getFixedSizeInBits() function
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| H A D | SelectionDAGNodes.h | 206 return getValueType().getScalarType().getFixedSizeInBits();
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2606 size_t DestLaneSize = VecT.getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2614 Src1.getValueType().getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2621 Src2.getValueType().getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2679 size_t DestLaneSize = VecT.getVectorElementType().getFixedSizeInBits(); in LowerBUILD_VECTOR()
3255 SetCCVector.getValueType().getVectorElementType().getFixedSizeInBits(); in performBitcastCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1253 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 894 if (LI->getAlign() < VT.getFixedSizeInBits() / 8 && in selectLoad()
926 if (SI->getAlign() < VT.getFixedSizeInBits() / 8 && in selectStore()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 2033 EltVT.getFixedSizeInBits() / 8)); in SplitVecRes_INSERT_VECTOR_ELT()
3907 commonAlignment(SmallestAlign, EltVT.getFixedSizeInBits() / 8)); in SplitVecOp_EXTRACT_VECTOR_ELT()
7171 unsigned EltSize = EltVT.getFixedSizeInBits(); in WidenVecOp_BITCAST()
7260 SubVT.getFixedSizeInBits()) in WidenVecOp_INSERT_SUBVECTOR()
7869 if (RetVT.getFixedSizeInBits() < MemVTWidth || MemVT == WidenVT) in findMemType()
8160 unsigned ValEltWidth = ValEltVT.getFixedSizeInBits(); in GenWidenVectorStores()
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| H A D | TargetLowering.cpp | 10522 unsigned NumBits = NewStoredVT.getFixedSizeInBits(); in expandUnalignedStore()
10588 APInt(AddrVT.getFixedSizeInBits(), in IncrementMemoryAddress()
10614 DAG.getVScale(dl, IdxVT, APInt(IdxVT.getFixedSizeInBits(), NElts)); in clampDynamicVectorIndex()
10650 unsigned EltSize = EltVT.getFixedSizeInBits() / 8; // FIXME: should be ABI size. in getVectorSubVecPointer()
10651 assert(EltSize * 8 == EltVT.getFixedSizeInBits() && in getVectorSubVecPointer()
11093 unsigned LoSize = VT.getFixedSizeInBits(); in forceExpandWideMUL()
11887 APInt(PtrVT.getFixedSizeInBits(), VT.getStoreSize().getKnownMinValue())); in expandVectorSplice()
11910 APInt(PtrVT.getFixedSizeInBits(), in expandVectorSplice()
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| H A D | SelectionDAGBuilder.cpp | 459 const uint64_t ValueSize = ValueVT.getFixedSizeInBits(); in getCopyFromPartsVector()
742 uint64_t ValueSize = ValueVT.getFixedSizeInBits(); in getCopyToPartsVector()
743 assert(PartVT.getFixedSizeInBits() > ValueSize && in getCopyToPartsVector()
8013 if (Mask.getValueType().getFixedSizeInBits() < MemVT.getFixedSizeInBits()) { in visitIntrinsicCall()
8018 DAG.getShiftAmountConstant(Mask.getValueType().getFixedSizeInBits(), in visitIntrinsicCall()
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| H A D | DAGCombiner.cpp | 1117 N1.getValueType().getFixedSizeInBits() <= 64) { in reassociationCanBreakAddressingModePattern()
7788 LHS.getOperand(0).getValueType().getFixedSizeInBits())) in visitAND()
20003 DAG.getConstant(APInt::getLowBitsSet(STType.getFixedSizeInBits(), in ForwardStoreValueToDirectLoad()
22657 if (STBase.contains(DAG, ST->getMemoryVT().getFixedSizeInBits(), in visitSTORE()
22659 ST1->getMemoryVT().getFixedSizeInBits())) { in visitSTORE()
24156 uint64_t VTSize = VT.getFixedSizeInBits(); in createBuildVecShuffle()
24157 uint64_t InVT1Size = InVT1.getFixedSizeInBits(); in createBuildVecShuffle()
24158 uint64_t InVT2Size = InVT2.getFixedSizeInBits(); in createBuildVecShuffle()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2757 if (VT.getVectorNumElements() > 1024 || VT.getFixedSizeInBits() > 1024 * 8) in useRVVForFixedLengthVectorVT()
4357 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in lowerBUILD_VECTOR()
5423 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in lowerShuffleViaVRegSplitting()
5657 unsigned ElementSize = ScalarVT.getFixedSizeInBits(); in tryWidenMaskForShuffle()
8696 LLT(Ty.getSimpleVT()), Align(Ty.getFixedSizeInBits() / 8)); in getAddr()
8726 LLT(Ty.getSimpleVT()), Align(Ty.getFixedSizeInBits() / 8)); in getAddr()
8797 LLT(Ty.getSimpleVT()), Align(Ty.getFixedSizeInBits() / 8)); in getStaticTLSAddr()
9992 unsigned ElemsPerVReg = *VLEN / ElemVT.getFixedSizeInBits(); in lowerINSERT_VECTOR_ELT()
10220 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in lowerEXTRACT_VECTOR_ELT()
12134 APInt(PtrVT.getFixedSizeInBits(), in lowerVECTOR_INTERLEAVE()
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| H A D | RISCVTargetTransformInfo.cpp | 490 unsigned ElemsPerVReg = *VLen / ElemVT.getFixedSizeInBits(); in costShuffleViaVRegSplitting()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2729 Align(std::min(PtrVT.getFixedSizeInBits(), VT.getFixedSizeInBits()) / 8)); in LowerVAARG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 392 switch (PowerOf2Ceil(VT.getFixedSizeInBits())) { in promoteScalarIntegerPTX()
5366 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
5372 if (OrigVT.getFixedSizeInBits() <= OptSize) { in IsMulWideOperandDemotable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3187 const uint64_t NumBits = ResultVT.getFixedSizeInBits(); in lowerCTLZResults()
4378 if (VT.getFixedSizeInBits() <= EltVT.getFixedSizeInBits()) { in performTruncateCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6943 if (ValVT.getFixedSizeInBits() < RegVT.getFixedSizeInBits()) in CC_AIX()
7129 assert(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits()); in truncateScalarIntegerArg()
7483 (ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) { in LowerFormalArguments_AIX()
7806 else if (Arg.getValueType().getFixedSizeInBits() < in LowerCall_AIX()
7807 LocVT.getFixedSizeInBits()) in LowerCall_AIX()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 2767 if (VA.getLocVT().getFixedSizeInBits() > in MatchingStackOffset()
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