| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.cpp | 629 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); in adjustCopiesBackFrom()
631 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); in adjustCopiesBackFrom()
823 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); in removeCopyByCommutingDef()
825 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); in removeCopyByCommutingDef()
1117 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); in removePartialRedundancy()
1119 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); in removePartialRedundancy()
1304 Register SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg(); in reMaterializeTrivialDef()
1306 Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg(); in reMaterializeTrivialDef()
1971 if (!MRI->isReserved(CP.getDstReg())) { in canJoinPhys()
2042 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy()
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| H A D | TargetFrameLoweringImpl.cpp | 196 CS.getDstReg()) in spillCalleeSavedRegister()
212 .addReg(CS.getDstReg(), getKillRegState(true)); in restoreCalleeSavedRegister()
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| H A D | RegisterCoalescer.h | 98 Register getDstReg() const { return DstReg; } in getDstReg() function
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| H A D | RegAllocPBQP.cpp | 444 if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg()) in apply()
447 Register DstReg = CP.getDstReg(); in apply()
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| H A D | PrologEpilogInserter.cpp | 612 MCRegister DstReg = I.getDstReg(); in updateLiveness()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 108 Register getDstReg() const { return getOperand(0).getReg(); } in getDstReg() function
188 Register getDstReg() const { return getOperand(0).getReg(); } in getDstReg() function
399 Register getDstReg() const { return getReg(0); } in getDstReg() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaFrameLowering.cpp | 168 IsStoreInst = Info.getDstReg() == DstReg.asMCReg() && in emitPrologue()
256 IsRestoreInst = Info.getDstReg() == DstReg.asMCReg() && in emitEpilogue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86RegisterBankInfo.cpp | 367 bool IsFP = any_of(MRI.use_nodbg_instructions(cast<GLoad>(MI).getDstReg()), in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineFrameInfo.h | 64 MCRegister getDstReg() const { return DstReg; } in getDstReg() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 1215 unsigned SpilledReg = I.getDstReg(); in emitPrologue()
2429 auto &SpilledVSR = VSRContainingGPRs[Info.getDstReg()]; in spillCalleeSavedRegisters()
2487 unsigned Dst = I.getDstReg(); in spillCalleeSavedRegisters()
2661 unsigned Dst = CSI[i].getDstReg(); in restoreCalleeSavedRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragments.td | 529 LLT Ty = MRI.getType(Load.getDstReg());
548 LLT Ty = MRI.getType(Load.getDstReg());
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 869 LoadValsSinceLastStore.push_back(Ld->getDstReg()); in optimizeConsecutiveMemOpAddressing()
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| H A D | AArch64InstructionSelector.cpp | 4755 auto OpAndCC = emitOverflowOp(I.getOpcode(), CarryMI.getDstReg(), in selectOverflowOp()
5547 Register Dst = ExtLd.getDstReg(); in selectIndexedExtLoad()
5652 Register Dst = Ld.getDstReg(); in selectIndexedLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 782 Register LoadReg = LoadMI->getDstReg(); in matchCombineExtendingLoads()
981 if (!LoadMI || !MRI.hasOneNonDBGUse(LoadMI->getDstReg())) in matchCombineLoadWithAndMask()
984 Register LoadReg = LoadMI->getDstReg(); in matchCombineLoadWithAndMask()
1137 {MRI.getType(LoadDef->getDstReg()), in matchSextInRegOfLoad()
1142 MatchInfo = std::make_tuple(LoadDef->getDstReg(), NewSizeBits); in matchSextInRegOfLoad()
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| H A D | LegalizerHelper.cpp | 1620 Register DstReg = LoadMI.getDstReg(); in narrowScalar()
1638 Register DstReg = LoadMI.getDstReg(); in narrowScalar()
4048 Register DstReg = LoadMI.getDstReg(); in lowerLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 140 MCRegister getDstReg() const { return Dst; } in getDstReg() function in __anon730428320111::AArch64AsmParser::PrefixInfo
5419 if (Inst.getOperand(0).getReg() != Prefix.getDstReg()) in validateInstruction()
5427 isMatchingOrAlias(Prefix.getDstReg(), Inst.getOperand(i).getReg())) in validateInstruction()
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