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Searched refs:fixed_vector (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp69 const LLT v16s64 = LLT::fixed_vector(16, 64); in SPIRVLegalizerInfo()
70 const LLT v16s32 = LLT::fixed_vector(16, 32); in SPIRVLegalizerInfo()
71 const LLT v16s16 = LLT::fixed_vector(16, 16); in SPIRVLegalizerInfo()
72 const LLT v16s8 = LLT::fixed_vector(16, 8); in SPIRVLegalizerInfo()
73 const LLT v16s1 = LLT::fixed_vector(16, 1); in SPIRVLegalizerInfo()
75 const LLT v8s64 = LLT::fixed_vector(8, 64); in SPIRVLegalizerInfo()
76 const LLT v8s32 = LLT::fixed_vector(8, 32); in SPIRVLegalizerInfo()
77 const LLT v8s16 = LLT::fixed_vector(8, 16); in SPIRVLegalizerInfo()
78 const LLT v8s8 = LLT::fixed_vector(8, 8); in SPIRVLegalizerInfo()
79 const LLT v8s1 = LLT::fixed_vector(8, 1); in SPIRVLegalizerInfo()
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H A DSPIRVPreLegalizer.cpp332 NewT = LLT::fixed_vector(2, NewT); in createNewIdReg()
351 NewT = LLT::fixed_vector(2, NewT); in createNewIdReg()
H A DSPIRVBuiltins.cpp1366 LLT::fixed_vector(3, PointerSize)); in genWorkgroupQuery()
1441 LLT::fixed_vector(Call->ReturnType->getOperand(2).getImm(), BitWidth); in generateBuiltinVar()
1590 LLT::fixed_vector(NumActualRetComponents, 32)); in generateImageSizeQueryInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1907 if (Ty == LLT::fixed_vector(2, 64)) { in selectVectorSHL()
1909 } else if (Ty == LLT::fixed_vector(4, 32)) { in selectVectorSHL()
1911 } else if (Ty == LLT::fixed_vector(2, 32)) { in selectVectorSHL()
1913 } else if (Ty == LLT::fixed_vector(4, 16)) { in selectVectorSHL()
1915 } else if (Ty == LLT::fixed_vector(8, 16)) { in selectVectorSHL()
1917 } else if (Ty == LLT::fixed_vector(16, 8)) { in selectVectorSHL()
1919 } else if (Ty == LLT::fixed_vector(8, 8)) { in selectVectorSHL()
1961 if (Ty == LLT::fixed_vector(2, 64)) { in selectVectorAshrLshr()
1964 } else if (Ty == LLT::fixed_vector(4, 32)) { in selectVectorAshrLshr()
1967 } else if (Ty == LLT::fixed_vector(2, 32)) { in selectVectorAshrLshr()
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H A DAArch64PreLegalizerCombiner.cpp320 MidTy = LLT::fixed_vector(4, 32); in applyExtAddvToUdotAddv()
323 MidTy = LLT::fixed_vector(2, 32); in applyExtAddvToUdotAddv()
343 LLT MainTy = LLT::fixed_vector(16, 8); in applyExtAddvToUdotAddv()
355 Register v8Zeroes = Builder.buildConstant(LLT::fixed_vector(8, 8), 0) in applyExtAddvToUdotAddv()
361 .buildMergeLikeInstr(LLT::fixed_vector(16, 8), in applyExtAddvToUdotAddv()
366 .buildMergeLikeInstr(LLT::fixed_vector(16, 8), in applyExtAddvToUdotAddv()
373 extractParts(Ext1SrcReg, LLT::fixed_vector(16, 8), SrcNumElts / 16, in applyExtAddvToUdotAddv()
375 extractParts(Ext2SrcReg, LLT::fixed_vector(16, 8), SrcNumElts / 16, in applyExtAddvToUdotAddv()
386 ZeroesLLT = LLT::fixed_vector(4, 32); in applyExtAddvToUdotAddv()
389 ZeroesLLT = LLT::fixed_vector(2, 32); in applyExtAddvToUdotAddv()
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H A DAArch64LegalizerInfo.cpp52 const LLT v16s8 = LLT::fixed_vector(16, 8); in AArch64LegalizerInfo()
53 const LLT v8s8 = LLT::fixed_vector(8, 8); in AArch64LegalizerInfo()
54 const LLT v4s8 = LLT::fixed_vector(4, 8); in AArch64LegalizerInfo()
55 const LLT v2s8 = LLT::fixed_vector(2, 8); in AArch64LegalizerInfo()
56 const LLT v8s16 = LLT::fixed_vector(8, 16); in AArch64LegalizerInfo()
57 const LLT v4s16 = LLT::fixed_vector(4, 16); in AArch64LegalizerInfo()
58 const LLT v2s16 = LLT::fixed_vector(2, 16); in AArch64LegalizerInfo()
59 const LLT v2s32 = LLT::fixed_vector(2, 32); in AArch64LegalizerInfo()
60 const LLT v4s32 = LLT::fixed_vector(4, 32); in AArch64LegalizerInfo()
61 const LLT v2s64 = LLT::fixed_vector(2, 64); in AArch64LegalizerInfo()
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H A DAArch64PostLegalizerCombiner.cpp391 if (DstTy != LLT::fixed_vector(2, 64) && DstTy != LLT::fixed_vector(2, 32) && in matchCombineMulCMLT()
392 DstTy != LLT::fixed_vector(4, 32) && DstTy != LLT::fixed_vector(4, 16) && in matchCombineMulCMLT()
393 DstTy != LLT::fixed_vector(8, 16)) in matchCombineMulCMLT()
H A DAArch64PostLegalizerLowering.cpp1159 else if (DstTy == LLT::fixed_vector(2, 64)) { in matchExtMulToMULL()
1194 else if (DstTy == LLT::fixed_vector(2, 64)) { in applyExtMulToMULL()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LegalizerInfo.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86LegalizerInfo.cpp56 const LLT v2s32 = LLT::fixed_vector(2, 32); in X86LegalizerInfo()
57 const LLT v4s8 = LLT::fixed_vector(4, 8); in X86LegalizerInfo()
60 const LLT v16s8 = LLT::fixed_vector(16, 8); in X86LegalizerInfo()
61 const LLT v8s16 = LLT::fixed_vector(8, 16); in X86LegalizerInfo()
62 const LLT v4s32 = LLT::fixed_vector(4, 32); in X86LegalizerInfo()
63 const LLT v2s64 = LLT::fixed_vector(2, 64); in X86LegalizerInfo()
64 const LLT v2p0 = LLT::fixed_vector(2, p0); in X86LegalizerInfo()
66 const LLT v32s8 = LLT::fixed_vector(32, 8); in X86LegalizerInfo()
67 const LLT v16s16 = LLT::fixed_vector(16, 16); in X86LegalizerInfo()
68 const LLT v8s32 = LLT::fixed_vector(8, 32); in X86LegalizerInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCLegalizerInfo.cpp49 const LLT V16S8 = LLT::fixed_vector(16, 8); in PPCLegalizerInfo()
50 const LLT V8S16 = LLT::fixed_vector(8, 16); in PPCLegalizerInfo()
51 const LLT V4S32 = LLT::fixed_vector(4, 32); in PPCLegalizerInfo()
52 const LLT V2S64 = LLT::fixed_vector(2, 64); in PPCLegalizerInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp106 LLT::fixed_vector(Ty.getNumElements() + 1, EltTy)); in oneMoreElement()
136 return std::pair(TypeIdx, LLT::fixed_vector(NewNumElts, EltTy)); in moreEltsToNext32Bit()
158 return std::pair(TypeIdx, LLT::fixed_vector(NewNumElts, EltSize)); in moreElementsToNextExistingRegClass()
171 return LLT::fixed_vector(4, LLT::scalar(32)); in getBufferRsrcRegisterType()
173 return LLT::fixed_vector(NumElems * 4, LLT::scalar(32)); in getBufferRsrcRegisterType()
297 static const LLT V2S8 = LLT::fixed_vector(2, 8);
298 static const LLT V2S16 = LLT::fixed_vector(2, 16);
299 static const LLT V4S16 = LLT::fixed_vector(4, 16);
300 static const LLT V6S16 = LLT::fixed_vector(6, 16);
301 static const LLT V8S16 = LLT::fixed_vector(8, 16);
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H A DAMDGPUArgumentUsageInfo.cpp96 &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32)); in getPreloadedValue()
H A DAMDGPUPreLegalizerCombiner.cpp189 const LLT V2S16 = LLT::fixed_vector(2, 16); in applyClampI64ToI16()
H A DAMDGPURegisterBankInfo.cpp1051 return LLT::fixed_vector(128 / EltTy.getSizeInBits(), EltTy); in widen96To128()
1777 return B.buildMergeLikeInstr(LLT::fixed_vector(NumElts, S32), WideRegs) in handleD16VData()
2093 LLT MergeTy = LLT::fixed_vector(Ops.size(), EltTy); in foldInsertEltToCmpSelect()
2486 if (DstTy != LLT::scalar(16) && DstTy != LLT::fixed_vector(2, 16)) in applyMappingImpl()
2861 LLT Vec32 = LLT::fixed_vector(2 * SrcTy.getNumElements(), 32); in applyMappingImpl()
2976 LLT Vec32 = LLT::fixed_vector(2 * VecTy.getNumElements(), 32); in applyMappingImpl()
4112 if (DstTy == LLT::fixed_vector(2, 16)) { in getInstrMapping()
H A DAMDGPUInstructionSelector.cpp639 if (MRI->getType(Dst) != LLT::fixed_vector(2, 16) || in selectG_BUILD_VECTOR()
2230 if (DstTy == LLT::fixed_vector(2, 16) && SrcTy == LLT::fixed_vector(2, 32)) { in selectG_TRUNC()
3827 MRI.getType(Src) == LLT::fixed_vector(2, 16)) { in selectVOP3PModsImpl()
5374 LLT::fixed_vector(2, 16)); in isExtractHiElt()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DLowLevelType.h100 static constexpr LLT fixed_vector(unsigned NumElements, in fixed_vector() function
107 static constexpr LLT fixed_vector(unsigned NumElements, LLT ScalarTy) { in fixed_vector() function
260 return fixed_vector(Factor, *this); in multiplyElements()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp76 const LLT v16s8 = LLT::fixed_vector(16, 8); in MipsLegalizerInfo()
77 const LLT v8s16 = LLT::fixed_vector(8, 16); in MipsLegalizerInfo()
78 const LLT v4s32 = LLT::fixed_vector(4, 32); in MipsLegalizerInfo()
79 const LLT v2s64 = LLT::fixed_vector(2, 64); in MipsLegalizerInfo()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegacyLegalizerInfo.cpp348 IntermediateType = LLT::fixed_vector(Aspect.Type.getNumElements(), in findVectorLegalAction()
362 LLT::fixed_vector(NumElementsAndAction.first,
H A DLegalizeMutations.cpp104 TypeIdx, LLT::fixed_vector(NewNumElements, VecTy.getElementType())); in moreElementsToNextPow2()
H A DUtils.cpp537 LLT::fixed_vector(LeftoverNumElts, RegTy.getScalarSizeInBits()); in extractParts()
605 LLT NarrowTy = (NumElts == 1) ? EltTy : LLT::fixed_vector(NumElts, EltTy); in extractVectorParts()
632 LLT LeftoverTy = LLT::fixed_vector(LeftoverNumElts, EltTy); in extractVectorParts()
H A DLegalizerHelper.cpp3159 DstCastTy = LLT::fixed_vector(NumDstElt / NumSrcElt, DstEltTy); in lowerBitcast()
3171 SrcPartTy = LLT::fixed_vector(NumSrcElt / NumDstElt, SrcEltTy); in lowerBitcast()
4234 LLT NarrowTy = (NumElts == 1) ? EltTy : LLT::fixed_vector(NumElts, EltTy); in makeDstOps()
4887 LLT::fixed_vector(NarrowTy.getSizeInBits() / SrcScalSize, SrcScalSize); in fewerElementsBitcast()
5608 SrcExtTy = LLT::fixed_vector( in moreElementsVector()
5612 DstExtTy = LLT::fixed_vector( in moreElementsVector()
5630 LLT CondTy = LLT::fixed_vector( in moreElementsVector()
5724 LLT PaddedTy = LLT::fixed_vector(PaddedMaskNumElts, DestEltTy); in equalizeVectorShuffleLengths()
H A DCallLowering.cpp514 LLT BVType = LLT::fixed_vector(NumElts, PartLLT); in buildCopyFromRegs()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerInfo.h980 LLT NewTy = LLT::fixed_vector(NumElts, LLT::scalar(MinSize)); in widenVectorEltsToVectorMinSize()
1148 TypeIdx, LLT::fixed_vector(MinElements, VecTy.getElementType())); in clampMinNumElements()
1167 TypeIdx, LLT::fixed_vector(NewSize, VecTy.getElementType())); in alignNumElementsTo()
H A DLegalizationArtifactCombiner.h680 LLT NewBVTy = LLT::fixed_vector(NumSrcsUsed, SrcTy); in findValueFromBuildVector()

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