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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td22 !strconcat("f64.", !strconcat(name, "\t$dst, $src")),
23 !strconcat("f64.", name), f64Inst>;
33 !strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
34 !strconcat("f64.", name), f64Inst>;
43 !strconcat("f64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
44 !strconcat("f64.", name), f64Inst>;
77 def : Pat<(frint f64:$src), (NEAREST_F64 f64:$src)>;
81 def : Pat<(froundeven f64:$src), (NEAREST_F64 f64:$src)>;
99 def : Pat<(seteq f64:$lhs, f64:$rhs), (EQ_F64 f64:$lhs, f64:$rhs)>;
100 def : Pat<(setne f64:$lhs, f64:$rhs), (NE_F64 f64:$lhs, f64:$rhs)>;
[all …]
H A DWebAssemblyInstrConv.td193 "f64.convert_i32_s\t$dst, $src", "f64.convert_i32_s",
197 "f64.convert_i32_u\t$dst, $src", "f64.convert_i32_u",
209 "f64.convert_i64_s\t$dst, $src", "f64.convert_i64_s",
213 "f64.convert_i64_u\t$dst, $src", "f64.convert_i64_u",
218 "f64.promote_f32\t$dst, $src", "f64.promote_f32",
239 "f64.reinterpret_i64\t$dst, $src",
240 "f64.reinterpret_i64", 0xbf>;
/freebsd/lib/libc/arm/aeabi/
H A Daeabi_vfp_double.S38 vcmp.f64 d0, d1
47 vcmpe.f64 d0, d1
56 vcmpe.f64 d1, d0
65 vcmp.f64 d0, d1
77 vcmp.f64 d0, d1
89 vcmp.f64 d0, d1
101 vcmp.f64 d0, d1
113 vcmp.f64 d0, d1
125 vcmp.f64 d0, d1
142 vcvt.s32.f64 s0, d0
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVecFuncs.def70 TLI_DEFINE_VECFUNC("llvm.exp.f64", "_simd_exp_d2", FIXED(2), "_ZGV_LLVM_N2v")
76 TLI_DEFINE_VECFUNC("llvm.acos.f64", "_simd_acos_d2", FIXED(2), "_ZGV_LLVM_N2v")
80 TLI_DEFINE_VECFUNC("llvm.asin.f64", "_simd_asin_d2", FIXED(2), "_ZGV_LLVM_N2v")
85 TLI_DEFINE_VECFUNC("llvm.atan.f64", "_simd_atan_d2", FIXED(2), "_ZGV_LLVM_N2v")
92 TLI_DEFINE_VECFUNC("llvm.cos.f64", "_simd_cos_d2", FIXED(2), "_ZGV_LLVM_N2v")
97 TLI_DEFINE_VECFUNC("llvm.sin.f64", "_simd_sin_d2", FIXED(2), "_ZGV_LLVM_N2v")
102 TLI_DEFINE_VECFUNC("llvm.tan.f64", "_simd_tan_d2", FIXED(2), "_ZGV_LLVM_N2v")
112 TLI_DEFINE_VECFUNC("llvm.pow.f64", "_simd_pow_d2", FIXED(2), "_ZGV_LLVM_N2vv")
118 TLI_DEFINE_VECFUNC("llvm.sinh.f64", "_simd_sinh_d2", FIXED(2), "_ZGV_LLVM_N2v")
122 TLI_DEFINE_VECFUNC("llvm.cosh.f64", "_simd_cosh_d2", FIXED(2), "_ZGV_LLVM_N2v")
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td301 [(set f64:$XT, (load XForm:$addr))]>;
332 [(store f64:$XT, XForm:$addr)]>;
356 [(set f64:$XT, (any_fadd f64:$XA, f64:$XB))]>;
360 [(set f64:$XT, (any_fmul f64:$XA, f64:$XB))]>;
387 [(set f64:$XT, (any_fsub f64:$XA, f64:$XB))]>;
404 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>,
420 [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
436 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>,
452 [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
595 [(set f64:$XT, (any_fdiv f64:$XA, f64:$XB))]>;
[all …]
H A DPPCInstrSPE.td138 [(set f64:$RT, (fabs f64:$RA))]>;
142 [(set f64:$RT, (any_fadd f64:$RA, f64:$RB))]>;
146 [(set f64:$RT, (any_fpextend f32:$RB))]>;
153 [(set f64:$RT, (any_sint_to_fp i32:$RB))]>;
164 [(set f64:$RT, (any_uint_to_fp i32:$RB))]>;
192 [(set i32:$RT, (any_fp_to_sint f64:$RB))]>;
207 [(set i32:$RT, (any_fp_to_uint f64:$RB))]>;
211 [(set f64:$RT, (any_fdiv f64:$RA, f64:$RB))]>;
215 [(set f64:$RT, (any_fmul f64:$RA, f64:$RB))]>;
219 [(set f64:$RT, (fneg (fabs f64:$RA)))]>;
[all …]
H A DREADME_P9.txt202 [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
314 (set i128:$XT, (int_ppc_vsx_xscmpeqdp f64:$XA, f64:$XB))
315 (set i128:$XT, (int_ppc_vsx_xscmpgedp f64:$XA, f64:$XB))
316 (set i128:$XT, (int_ppc_vsx_xscmpgtdp f64:$XA, f64:$XB))
317 (set i128:$XT, (int_ppc_vsx_xscmpnedp f64:$XA, f64:$XB))
351 . (set f128:$XT, (PPCfcfids f64:$XB)) // xscvsdqp
352 (set f128:$XT, (PPCfcfidus f64:$XB)) // xscvudqp
390 (set f128:$vT, (int_ppc_vsx_xsiexpqp f128:$vA, f64:$vB))
394 . (set i64:$rT, (int_ppc_vsx_xsxexpdp f64$XB)) // xsxexpdp
395 (set i64:$rT, (int_ppc_vsx_xsxsigdp f64$XB)) // xsxsigdp
[all …]
H A DPPCInstrInfo.td20 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 SDTCisVT<0, f64>, SDTCisPtrTy<1>
26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
184 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
199 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
285 [SDTCisVT<0, f64>, SDTCisVT<1,i32>,
291 [SDTCisVT<0, i32>, SDTCisVT<1, f64>,
1270 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td32 // Handle all vector types as either f64 or v2f64.
33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
37 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
43 CCIfType<[f64], CCAssignToStack<8, 4>>,
58 // Handle all vector types as either f64 or v2f64.
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
62 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
73 // Handle all vector types as either f64 or v2f64.
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
[all …]
H A DARMInstrVFP.td14 def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
17 SDTCisVT<2, f64>]>;
99 def vfp_f64imm : Operand<f64>,
100 PatLeaf<(f64 fpimm), [{
156 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>,
191 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>,
428 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
429 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>,
453 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
454 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>,
[all …]
H A DARMInstrCDE.td552 def : Pat<(f64 (int_arm_cde_vcx1 timm:$coproc, timm:$imm)),
553 (f64 (CDE_VCX1_fpdp p_imm:$coproc, imm_11b:$imm))>;
554 def : Pat<(f64 (int_arm_cde_vcx1a timm:$coproc, (f64 DPR:$acc), timm:$imm)),
555 (f64 (CDE_VCX1A_fpdp p_imm:$coproc, DPR:$acc, imm_11b:$imm))>;
562 def : Pat<(f64 (int_arm_cde_vcx2 timm:$coproc, (f64 DPR:$n), timm:$imm)),
563 (f64 (CDE_VCX2_fpdp p_imm:$coproc, DPR:$n, imm_6b:$imm))>;
564 def : Pat<(f64 (int_arm_cde_vcx2a timm:$coproc, (f64 DPR:$acc), (f64 DPR:$n),
566 (f64 (CDE_VCX2A_fpdp p_imm:$coproc, DPR:$acc, DPR:$n, imm_6b:$imm))>;
576 def : Pat<(f64 (int_arm_cde_vcx3 timm:$coproc, (f64 DPR:$n), (f64 DPR:$m),
578 (f64 (CDE_VCX3_fpdp p_imm:$coproc, DPR:$n, DPR:$m, imm_3b:$imm))>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td18 def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
23 SDTCisVT<2, f64>]>;
59 def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>;
62 f64, FPR64INX, FPR32INX, FPR64INX, ?>;
64 f64, FPR64IN32X, FPR32INX, FPR64IN32X, ?>;
243 // f64 -> f32, f32 -> f64
251 // f64 -> f32, f32 -> f64
259 // f64 -> f32, f32 -> f64
284 def : PatFprFpr<fcopysign, FSGNJ_D, FPR64, f64>;
320 def : PatFprFpr<fcopysign, FSGNJ_D_INX, FPR64INX, f64>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallingConv.td54 // For hard-float, f128 values are returned as a pair of f64's rather than a
57 CCBitConvertToType<f64>,
90 CCIfType<[f64], CCAssignToStack<8, 8>>
107 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
109 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
110 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
157 // f64 arguments are passed in double precision FP registers.
158 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
165 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
180 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td77 def f64 : VTFP<64, 13>; // 64-bit floating point value
203 def v1f64 : VTVec<1, f64, 127>; // 1 x f64 vector value
204 def v2f64 : VTVec<2, f64, 128>; // 2 x f64 vector value
205 def v3f64 : VTVec<3, f64, 129>; // 3 x f64 vector value
206 def v4f64 : VTVec<4, f64, 130>; // 4 x f64 vector value
207 def v8f64 : VTVec<8, f64, 131>; // 8 x f64 vector value
208 def v16f64 : VTVec<16, f64, 132>; // 16 x f64 vector value
209 def v32f64 : VTVec<32, f64, 133>; // 32 x f64 vector value
210 def v64f64 : VTVec<64, f64, 134>; // 64 x f64 vector value
211 def v128f64 : VTVec<128, f64, 135>; // 128 x f64 vector value
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td230 defm : LdPat<load, FLD_D, f64>;
231 def : RegRegLdPat<load, FLDX_D, f64>;
235 defm : StPat<store, FST_D, FPR64, f64>;
236 def : RegRegStPat<store, FSTX_D, FPR64, f64>;
241 def : Pat<(f64 (loongarch_ftint FPR64:$src)), (FTINTRZ_L_D FPR64:$src)>;
244 // f64 -> f32
246 // f32 -> f64
247 def : Pat<(f64 (fpextend FPR32:$src)), (FCVT_D_S FPR32:$src)>;
285 def : Pat<(f64 fpimm0), (MOVGR2FR_D R0)>;
286 def : Pat<(f64 fpimm0ne
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td49 CCIfType<[f64], CCCustom<"CC_CSKY_ABIV2_SOFT_64">>,
50 CCIfType<[f64], CCAssignToStack<8, 4>>
59 CCIfType<[f64], CCCustom<"Ret_CSKY_ABIV2_SOFT_64">>
71 CCIfType<[f64], CCAssignToReg<[F0_64, F1_64, F2_64, F3_64]>>,
72 CCIfType<[f64], CCAssignToStack<8, 4>>
81 CCIfType<[f64], CCAssignToReg<[F0_64]>>
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/arm/
H A Dextendsfdf2vfp.S22 vcvt.f64.f32 d0, s0
25 vcvt.f64.f32 d7, s15 // convert single to double
H A Dtruncdfsf2vfp.S22 vcvt.f32.f64 s0, d0
25 vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
H A Dfixdfsivfp.S22 vcvt.s32.f64 s0, d0
26 vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15
H A Dfixunsdfsivfp.S23 vcvt.u32.f64 s0, d0
27 vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15
H A Dfloatsidfvfp.S23 vcvt.f64.s32 d0, s0
26 vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
H A Dfloatunssidfvfp.S23 vcvt.f64.u32 d0, s0
26 vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
H A Ddivdf3vfp.S21 vdiv.f64 d0, d0, d1
25 vdiv.f64 d5, d6, d7
H A Dmuldf3vfp.S21 vmul.f64 d0, d0, d1
25 vmul.f64 d6, d6, d7
H A Dsubdf3vfp.S21 vsub.f64 d0, d0, d1
25 vsub.f64 d6, d6, d7

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