1*0b57cec5SDimitry Andric//===-- fixdfsivfp.S - Implement fixdfsivfp -----------------------===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andric#include "../assembly.h" 10*0b57cec5SDimitry Andric 11*0b57cec5SDimitry Andric// 12*0b57cec5SDimitry Andric// extern int __fixdfsivfp(double a); 13*0b57cec5SDimitry Andric// 14*0b57cec5SDimitry Andric// Converts double precision float to a 32-bit int rounding towards zero. 15*0b57cec5SDimitry Andric// Uses Darwin calling convention where a double precision parameter is 16*0b57cec5SDimitry Andric// passed in GPR register pair. 17*0b57cec5SDimitry Andric// 18*0b57cec5SDimitry Andric .syntax unified 19*0b57cec5SDimitry Andric .p2align 2 20*0b57cec5SDimitry AndricDEFINE_COMPILERRT_FUNCTION(__fixdfsivfp) 21*0b57cec5SDimitry Andric#if defined(COMPILER_RT_ARMHF_TARGET) 22*0b57cec5SDimitry Andric vcvt.s32.f64 s0, d0 23*0b57cec5SDimitry Andric vmov r0, s0 24*0b57cec5SDimitry Andric#else 25*0b57cec5SDimitry Andric vmov d7, r0, r1 // load double register from R0/R1 26*0b57cec5SDimitry Andric vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15 27*0b57cec5SDimitry Andric vmov r0, s15 // move s15 to result register 28*0b57cec5SDimitry Andric#endif 29*0b57cec5SDimitry Andric bx lr 30*0b57cec5SDimitry AndricEND_COMPILERRT_FUNCTION(__fixdfsivfp) 31*0b57cec5SDimitry Andric 32*0b57cec5SDimitry AndricNO_EXEC_STACK_DIRECTIVE 33*0b57cec5SDimitry Andric 34