Home
last modified time | relevance | path

Searched refs:f16 (Results 1 – 25 of 170) sorted by relevance

1234567

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfh.td56 f16, FPR16, FPR32, ?, FPR16>;
58 f16, FPR16, FPR32, ?, FPR16>;
66 f16, FPR16INX, FPR32INX, ?, FPR16INX>;
69 f16, FPR16INX, FPR32INX, ?, FPR16INX>;
294 def : Pat<(f16 (any_fsqrt FPR16:$rs1)), (FSQRT_H FPR16:$rs1, FRM_DYN)>;
296 def : Pat<(f16 (fneg FPR16:$rs1)), (FSGNJN_H $rs1, $rs1)>;
297 def : Pat<(f16 (fabs FPR16:$rs1)), (FSGNJX_H $rs1, $rs1)>;
299 def : Pat<(riscv_fclass (f16 FPR16:$rs1)), (FCLASS_H $rs1)>;
301 def : PatFprFpr<fcopysign, FSGNJ_H, FPR16, f16>;
302 def : PatFprFpr<riscv_fsgnjx, FSGNJX_H, FPR16, f16>;
[all …]
H A DRISCVInstrInfoZfa.td299 def: Pat<(f16 (riscv_fli timm:$imm)), (FLI_H timm:$imm)>;
301 def: PatFprFpr<fminimum, FMINM_H, FPR16, f16>;
302 def: PatFprFpr<fmaximum, FMAXM_H, FPR16, f16>;
306 def: Pat<(f16 (any_frint FPR16:$rs1)), (FROUNDNX_H FPR16:$rs1, FRM_DYN)>;
309 def: Pat<(f16 (any_fnearbyint FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_DYN)>;
311 def: Pat<(f16 (any_fround FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RMM)>;
312 def: Pat<(f16 (any_froundeven FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RNE)>;
313 def: Pat<(f16 (any_ffloor FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RDN)>;
314 def: Pat<(f16 (any_fceil FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RUP)>;
315 def: Pat<(f16 (any_ftrunc FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RTZ)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrVFP.td62 def vfp_f16imm : Operand<f16>,
63 PatLeaf<(f16 fpimm), [{
184 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>,
219 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>,
459 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
460 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
484 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
485 [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
505 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
506 [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
[all …]
/freebsd/crypto/openssl/crypto/aes/asm/
H A Daest4-sparcv9.pl136 ldd [$key + 32], %f16
147 aes_eround01 %f16, %f4, %f2, %f0
149 ldd [$key + 16], %f16
157 aes_eround01_l %f16, %f4, %f2, %f0
214 ldd [$key + 32], %f16
225 aes_dround01 %f16, %f4, %f2, %f0
227 ldd [$key + 16], %f16
235 aes_dround01_l %f16, %f4, %f2, %f0
608 aes_eround01 %f16, %f0, %f2, %f4
610 ldd [$key + 208], %f16
[all …]
/freebsd/crypto/openssl/crypto/camellia/asm/
H A Dcmllt4-sparcv9.pl103 ldd [$key + 32], %f16
120 camellia_f %f16, %f2, %f0, %f2
121 ldd [$key + 16], %f16
138 camellia_f %f16, %f2, %f0, %f2
198 ldd [$key - 24], %f16
215 camellia_f %f16, %f2, %f0, %f2
216 ldd [$key - 24], %f16
233 camellia_f %f16, %f2, %f0, %f2
349 ldd [%o4 + 0], %f16
354 camellia_f %f16, %f2, %f0, %f2
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td84 def f16 : VTFP<16, 11>; // 16-bit floating point value
173 def v1f16 : VTVec<1, f16, 91>; // 1 x f16 vector value
174 def v2f16 : VTVec<2, f16, 92>; // 2 x f16 vector value
175 def v3f16 : VTVec<3, f16, 93>; // 3 x f16 vector value
176 def v4f16 : VTVec<4, f16, 94>; // 4 x f16 vector value
177 def v8f16 : VTVec<8, f16, 95>; // 8 x f16 vector value
178 def v16f16 : VTVec<16, f16, 96>; // 16 x f16 vector value
179 def v32f16 : VTVec<32, f16, 97>; // 32 x f16 vector value
180 def v64f16 : VTVec<64, f16, 98>; // 64 x f16 vector value
181 def v128f16 : VTVec<128, f16, 99>; // 128 x f16 vector value
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td25 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
29 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
33 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
40 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
49 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
54 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
66 CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg<
137 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
141 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<
144 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
[all …]
H A DVINTERPInstructions.td138 defm V_INTERP_P10_F16_F32_inreg : VINTERP_t16<"v_interp_p10_f16_f32", [f32, f16, f32, f16]>;
139 defm V_INTERP_P2_F16_F32_inreg : VINTERP_t16<"v_interp_p2_f16_f32", [f16, f16, f32, f32]>;
143 defm V_INTERP_P10_RTZ_F16_F32_inreg : VINTERP_t16<"v_interp_p10_rtz_f16_f32", [f32, f16, f32, f16]>;
144 defm V_INTERP_P2_RTZ_F16_F32_inreg : VINTERP_t16 <"v_interp_p2_rtz_f16_f32", [f16, f16, f32, f32]>;
192 (f16 (EXTRACT_SUBREG VGPR_32:$src0, !if(high, hi16, lo16))),
196 (f16 (EXTRACT_SUBREG VGPR_32:$src2, !if(high, hi16, lo16)))),
214 V_INTERP_P2_F16_F32_inreg_t16, f16, 1>;
218 V_INTERP_P2_RTZ_F16_F32_inreg_t16, f16, 1>;
226 V_INTERP_P2_F16_F32_inreg_fake16, f16,
232 V_INTERP_P2_RTZ_F16_F32_inreg_fake16, f16,
H A DSIInstructions.td279 def : GCNPat <(f16 (fptrunc_round f32:$src0, (i32 SupportedRoundMode:$round))),
283 def : GCNPat <(f16 (fptrunc_round f32:$src0, (i32 SupportedRoundMode:$round))),
287 def : GCNPat <(f16 (fptrunc_round (f32 (VOP3OpSelMods f32:$src0, i32:$src0_modifiers)), (i32 Suppor…
1250 (f64 (any_fpextend f16:$src)),
1255 (i32 (fp_to_sint f16:$src)),
1260 (i32 (fp_to_uint f16:$src)),
1265 (f16 (sint_to_fp i32:$src)),
1270 (f16 (uint_to_fp i32:$src)),
1327 def : FMADPat <f16, V_MAC_F16_e64>;
1359 def : VOPSelectPat <f16>;
[all …]
H A DVOP3PInstructions.td30 // Their operands are only sort of f16 operands. Depending on
32 // values are really f16 converted to f32, so we treat these as f16
158 // At least one of the operands needs to be an fpextend of an f16
162 (f32 (fma_like (f32 (VOP3PMadMixModsExt f16:$src0, i32:$src0_mods)),
163 (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_mods)),
164 (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_mods)))),
168 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
169 (f32 (VOP3PMadMixModsExt f16:$src1, i32:$src1_mods)),
174 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
176 (f32 (VOP3PMadMixModsExt f16:$src2, i32:$src2_mods)))),
[all …]
H A DVOPCInstructions.td493 defm VOPC_I1_F16_F16 : VOPC_Profile_t16<[Write32Bit], f16>;
500 defm VOPC_F16_F16 : VOPC_NoSdst_Profile_t16<[Write32Bit], f16>;
905 def NAME : VOPC_Class_Profile<sched, f16>;
906 def _t16 : VOPC_Class_Profile_Base<sched, f16, f16> {
935 def _fake16 : VOPC_Class_Profile_Base<sched, f16, f16> {
976 def NAME : VOPC_Class_NoSdst_Profile<sched, f16>;
977 def _t16 : VOPC_Class_NoSdst_Profile<sched, f16, f16> {
1004 def _fake16 : VOPC_Class_NoSdst_Profile<sched, f16, f16> {
1051 0 /* src1_modifiers */, (f16 (EXTRACT_SUBREG VGPR_32:$src1, lo16)),
1382 defm : FCMP_Pattern <COND_O, V_CMP_O_F16_t16_e64, f16>;
[all …]
H A DAMDGPUCombine.td39 (match (G_FSQRT f16:$sqrt, $x, (MIFlags FmContract)),
40 (G_FDIV f16:$dst, $y, $sqrt, (MIFlags FmContract)):$root,
155 // For gfx8, expand f16-fmed3-as-f32 into a min/max f16 sequence. This
H A DSIRegisterInfo.td345 def M0_CLASS_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16, (add M0_LO16)> {
354 def SGPR_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,
362 def SGPR_HI16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,
371 def SGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,
427 def TTMP_LO16 : SIRegisterClass<"AMDGPU", [i16, f16, bf16], 16,
553 def Reg16Types : RegisterTypes<[i16, f16, bf16]>;
601 // i16/f16 only on VI+
669 def AGPR_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,
721 def Pseudo_SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16], 32,
746 def SReg_32_XM0_XEXEC : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, …
[all …]
/freebsd/crypto/openssl/crypto/des/asm/
H A Ddest4-sparcv9.pl80 des_kexpand %f14, 1, %f16
82 des_kexpand %f16, 3, %f20
84 des_kexpand %f16, 2, %f18
85 std %f16, [$out + 0x40]
135 ldd [$key + 0x30], %f16
166 des_round %f16, %f18, %f0, %f0
236 ldd [$key + 0x48], %f16
266 des_round %f16, %f18, %f0, %f0
344 ldd [$key + 0x30], %f16
375 des_round %f16, %f18, %f0, %f0
[all …]
/freebsd/crypto/openssl/crypto/sha/asm/
H A Dsha1-sparcv9.pl229 ldd [%o1 + 0x20], %f16
258 ldd [%o1 + 0x18], %f16
270 faligndata %f14, %f16, %f12
271 faligndata %f16, %f18, %f14
272 faligndata %f18, %f20, %f16
H A Dsha512-sparcv9.pl506 ldd [%o1 + 0x00], %f16
570 faligndata %f18, %f20, %f16
612 ldd [%o1 + 0x20], %f16
644 ldd [%o1 + 0x18], %f16
656 faligndata %f14, %f16, %f12
657 faligndata %f16, %f18, %f14
658 faligndata %f18, %f20, %f16
/freebsd/crypto/openssl/crypto/md5/asm/
H A Dmd5-sparcv9.pl247 ldd [%o1 + 0x20], %f16
277 ldd [%o1 + 0x18], %f16
289 faligndata %f14, %f16, %f12
290 faligndata %f16, %f18, %f14
291 faligndata %f18, %f20, %f16
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp121 if (OpVT == MVT::f16) { in getFPEXT()
156 if (RetVT == MVT::f16) { in getFPROUND()
203 if (OpVT == MVT::f16) { in getFPTOSINT()
252 if (OpVT == MVT::f16) { in getFPTOUINT()
302 if (RetVT == MVT::f16) in getSINTTOFP()
317 if (RetVT == MVT::f16) in getSINTTOFP()
330 if (RetVT == MVT::f16) in getSINTTOFP()
350 if (RetVT == MVT::f16) in getUINTTOFP()
365 if (RetVT == MVT::f16) in getUINTTOFP()
378 if (RetVT == MVT::f16) in getUINTTOFP()
[all …]
/freebsd/lib/libc/powerpc/gen/
H A D_setjmp.S61 stfd %f16,112+2*8(%r3)
88 lfd %f16,112+2*8(%r3)
H A Dsetjmp.S71 stfd %f16,112+2*8(%r6)
99 lfd %f16,112+2*8(%r3)
H A Dsigsetjmp.S76 stfd %f16,112+2*8(%r6)
103 lfd %f16,112+2*8(%r3)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td16 def f16imm : Operand<f16>;
198 def F16RT : RegTyInfo<f16, B16, "f16", f16imm, fpimm, supports_imm = 0>;
335 OpcStr # "$ftz" # nan_str # ".f16",
336 [(set f16:$dst, (OpNode f16:$a, f16:$b))]>,
397 op_str # "$ftz.f16",
398 [(set f16:$dst, (op_pat f16:$a, f16:$b))]>,
462 def f16 : BasicFlagsNVPTXInst<(outs B16:$dst), (ins B16:$a),
464 OpcStr # "$ftz.f16",
465 [(set f16:$dst, (OpNode f16:$a))]>,
531 "cvt${mode:base}${mode:ftz}${mode:sat}." # ToType # ".f16">,
[all …]
/freebsd/contrib/arm-optimized-routines/math/aarch64/sve/
H A Dlog1p.c97 f8 = svmul_x (pg, f4, f4), f16 = svmul_x (pg, f8, f8); in SV_NAME_D1() local
98 svfloat64_t p = sv_estrin_18_f64_x (pg, f, f2, f4, f8, f16, d->poly); in SV_NAME_D1()
/freebsd/usr.sbin/bsdconfig/console/
H A Dfont174 [ "$f8" -a "$f14" -a "$f16" ] || f_die 1 "$msg_unknown_font_selection"
178 f_eval_catch "$0" f_sysrc_set 'f_sysrc_set font8x16 "%s"' "$f16" || f_die
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp162 addRegisterClass(MVT::f16, &Mips::MSA128HRegClass); in MipsSETargetLowering()
163 setOperationAction(ISD::SETCC, MVT::f16, Promote); in MipsSETargetLowering()
164 setOperationAction(ISD::BR_CC, MVT::f16, Promote); in MipsSETargetLowering()
165 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); in MipsSETargetLowering()
166 setOperationAction(ISD::SELECT, MVT::f16, Promote); in MipsSETargetLowering()
167 setOperationAction(ISD::FADD, MVT::f16, Promote); in MipsSETargetLowering()
168 setOperationAction(ISD::FSUB, MVT::f16, Promote); in MipsSETargetLowering()
169 setOperationAction(ISD::FMUL, MVT::f16, Promote); in MipsSETargetLowering()
170 setOperationAction(ISD::FDIV, MVT::f16, Promote); in MipsSETargetLowering()
171 setOperationAction(ISD::FREM, MVT::f16, Promote); in MipsSETargetLowering()
[all …]

1234567