| /freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/MSF/ |
| H A D | MSFCommon.h | 132 return divideCeil(NumBytes, BlockSize); in bytesToBlocks()
163 return divideCeil(NumBlocks - FpmNumber, BlockSize); in getNumFpmIntervals()
168 return divideCeil(NumBlocks, 8 * BlockSize); in getNumFpmIntervals()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 403 constexpr T divideCeil(U Numerator, V Denominator) { in divideCeil() function
410 constexpr uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator) { in divideCeil() function
489 T CeilDiv = divideCeil(Value, Align); in alignTo()
496 uint64_t CeilDiv = divideCeil(Value, Align); in alignTo()
538 T CeilDiv = divideCeil(Value, Align); in alignTo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUImageIntrinsicOptimizer.cpp | 213 unsigned NumVDataLoads = divideCeil(NumElts, isD16 ? 2 : 1) * NumLoads; in optimizeSection()
215 unsigned NumVDataMsaas = divideCeil(4, isD16 ? 2 : 1) * NumMsaas; in optimizeSection()
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| H A D | AMDGPUPerfHintAnalysis.cpp | 228 unsigned Size = divideCeil(Ty->getPrimitiveSizeInBits(), 32); in visit()
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| H A D | AMDGPUSubtarget.cpp | 386 const unsigned MaxGroupNumWaves = divideCeil(MaxWorkGroupSize, WaveSize); in getOccupancyWithLocalMemSize()
390 MaxWaves = divideCeil(MaxWaves, getEUsPerCU()); in getOccupancyWithLocalMemSize()
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| H A D | AMDGPUAsmPrinter.cpp | 1196 ? divideCeil(CurrentProgramInfo.LDSBlocks, 2) in EmitProgramInfoSI()
1281 ? divideCeil(CurrentProgramInfo.LDSBlocks, 2) in EmitPALMetadata()
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| H A D | R600ControlFlowFinalizer.cpp | 131 unsigned CurrentStackSize = CurrentEntries + divideCeil(CurrentSubEntries, 4); in updateMaxStackSize()
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| H A D | SIRegisterInfo.cpp | 621 unsigned NumRegs = divideCeil(getRegSizeInBits(*RC), 32); in getReservedRegs()
698 unsigned NumRegs = divideCeil(getRegSizeInBits(*RC), 32); in getReservedRegs()
712 unsigned NumRegs = divideCeil(getRegSizeInBits(*RC), 32); in getReservedRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/DebugInfo/MSF/ |
| H A D | MSFCommon.cpp | 79 FL.Length = divideCeil(Msf.SB->NumBlocks, 8); in getFpmStreamLayout()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | DataLayout.cpp | 751 return divideCeil(getPointerAlignElem(AS).TypeBitWidth, 8); in getPointerSize()
758 std::max(MaxIndexSize, (unsigned)divideCeil(P.TypeBitWidth, 8)); in getMaxIndexSize()
771 return divideCeil(getPointerAlignElem(AS).IndexBitWidth, 8); in getIndexSize()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CmovConversion.cpp | 391 divideCeil(TrueOpDepth * 3 + FalseOpDepth, 4), in getDepthOfOptCmov()
392 divideCeil(FalseOpDepth * 3 + TrueOpDepth, 4)); in getDepthOfOptCmov()
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| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | FoldingSet.cpp | 48 unsigned NumInserts = 1 + divideCeil(Size, 4); in AddString()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | DataLayout.h | 474 return {divideCeil(BaseSize.getKnownMinValue(), 8), BaseSize.isScalable()}; in getTypeStoreSize()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 301 AddrWords += divideCeil(AddrComponents, 2); in getAddrSizeMIMGOp()
977 return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize), in getWavesPerEUForWorkGroup()
992 return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI)); in getWavesPerWorkGroup()
1094 return divideCeil(std::max(1u, NumRegs), Granule); in getGranulatedNumRegisterBlocks()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CodeGenTBAA.cpp | 381 llvm::divideCeil(CurrentBitFieldSize, Context.getCharWidth()); in CollectFields()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 441 divideCeil(Mask.size(), in getShuffleCost()
1908 return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock); in getRegUsageForType()
1911 return divideCeil(Size, ST->getRealMinVLen()); in getRegUsageForType()
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| /freebsd/contrib/llvm-project/lldb/source/API/ |
| H A D | SBType.cpp | 145 return llvm::divideCeil(bit_align.value_or(0), 8); in GetByteAlign()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | BasicTTIImpl.h | 1454 unsigned NumLegalInsts = divideCeil(VecTySize, VecTyLTSize);
1458 unsigned NumEltsPerLegalInst = divideCeil(NumElts, NumLegalInsts);
1468 Cost = divideCeil(UsedInsts.count() * *Cost.getValue(), NumLegalInsts);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetTransformInfo.cpp | 1272 unsigned NumDstVecs = divideCeil(VF * getScalarSizeInBits(VecTy), 128U); in getInterleavedMemoryOpCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AssignmentTrackingAnalysis.cpp | 2521 uint64_t SizeInBytes = divideCeil(SizeInBits, 8); in removeRedundantDbgLocsUsingBackwardScan()
2548 uint64_t EndInBytes = divideCeil(Fragment.endInBits(), 8); in removeRedundantDbgLocsUsingBackwardScan()
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| H A D | TargetLoweringBase.cpp | 1562 divideCeil(VT.getVectorElementCount().getKnownMinValue(), in getVectorTypeBreakdown()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | Scalarizer.cpp | 558 Split.NumFragments = divideCeil(NumElems, Split.NumPacked); in getVectorSplit()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 495 divideCeil(DstEltTy.getSizeInBits(), PartLLT.getSizeInBits()); in buildCopyFromRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfCompileUnit.cpp | 1716 divideCeil(Btr.BitSize, 8)); in createBaseTypeDIEs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1284 usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1287 usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1290 usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
3087 int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1; in updateGprCountSymbols()
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