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Searched refs:div_mask (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/arm/freescale/vybrid/
H A Dvf_ccm.c156 uint32_t div_mask; member
168 .div_mask = IPG_CLK_DIV_MASK,
192 .div_mask = PLL4_CLK_DIV_MASK,
204 .div_mask = SAI3_DIV_MASK,
216 .div_mask = CKO1_DIV_MASK,
228 .div_mask = ESDHC0_DIV_M,
240 .div_mask = ESDHC1_DIV_M,
252 .div_mask = 0,
264 .div_mask = 0x7,
276 .div_mask = 0,
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/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_composite.c48 uint32_t div_mask; member
181 div = ((reg & sc->div_mask) >> sc->div_shift); in rk_clk_composite_recalc()
204 for (div_reg = 0; div_reg <= ((sc->div_mask >> sc->div_shift) + 1); in rk_clk_composite_find_best()
278 dprintf(" div_mask: 0x%X, div_shift: %d\n", sc->div_mask, in rk_clk_composite_set_freq()
283 val |= sc->div_mask << RK_CLK_COMPOSITE_MASK_SHIFT; in rk_clk_composite_set_freq()
327 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_composite_register()
H A Drk_clk_armclk.c46 uint32_t div_mask; member
132 div = ((reg & sc->div_mask) >> sc->div_shift) + 1; in rk_clk_armclk_recalc()
194 val |= sc->div_mask << RK_ARMCLK_WRITE_MASK_SHIFT; in rk_clk_armclk_set_freq()
239 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_armclk_register()
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c63 uint32_t div_mask; member
525 uint32_t div_mask; member
565 sc->divider = (reg & sc->div_mask) + 2; in periph_init()
661 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
685 sc->div_mask = (1 <<clkdef->div_width) - 1; in periph_register()
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c58 uint32_t div_mask; member
638 uint32_t div_mask; member
678 sc->divider = (reg & sc->div_mask) + 2; in periph_init()
775 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
799 sc->div_mask = (1 <<clkdef->div_width) - 1; in periph_register()