Home
last modified time | relevance | path

Searched refs:div2 (Results 1 – 20 of 20) sorted by relevance

/freebsd/sys/arm/mv/clk/
H A Dperiph_clk_d.c67 struct clk_div_def *div2; in a37x0_periph_d_register_full_clk_dd() local
73 div2 = &device_def->clk_def.full_dd.div2; in a37x0_periph_d_register_full_clk_dd()
91 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
92 error = a37x0_periph_create_div(clkdom, div2, in a37x0_periph_d_register_full_clk_dd()
98 parent_names[1] = div2->clkdef.name; in a37x0_periph_d_register_full_clk_dd()
230 struct clk_div_def *div2; in a37x0_periph_d_register_mdd() local
236 div2 = &device_def->clk_def.mdd.div2; in a37x0_periph_d_register_mdd()
252 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_mdd()
253 error = a37x0_periph_create_div(clkdom, div2, in a37x0_periph_d_register_mdd()
260 parent_names[1] = div2->clkdef.name; in a37x0_periph_d_register_mdd()
H A Dperiph.h79 .clk_def.full_dd.div2.clkdef.name = _div2_name, \
80 .clk_def.full_dd.div2.offset = _div2_reg, \
81 .clk_def.full_dd.div2.i_shift = _div2_shift, \
82 .clk_def.full_dd.div2.i_width = 0x3, \
83 .clk_def.full_dd.div2.f_shift = 0x0, \
84 .clk_def.full_dd.div2.f_width = 0x0, \
85 .clk_def.full_dd.div2.div_flags = 0x0, \
86 .clk_def.full_dd.div2.div_table = NULL, \
197 .clk_def.mdd.div2.clkdef.name = _div2_name, \
198 .clk_def.mdd.div2.offset = _div2_reg, \
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqoriq-clock.txt165 clock-output-names = "pll0", "pll0-div2";
173 clock-output-names = "pll1", "pll1-div2";
181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
199 clock-output-names = "platform-pll", "platform-pll-div2";
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih410-clock.dtsi136 clock-output-names = "clk-m-a9-ext2f-div2";
H A Dstih418-clock.dtsi136 clock-output-names = "clk-m-a9-ext2f-div2";
H A Dstih407-clock.dtsi131 clock-output-names = "clk-m-a9-ext2f-div2";
/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt21 - adi,reference-div2-enable: Enables reference divider.
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXCV.td465 def CV_CPLXMUL_R_DIV2 : CVSIMDRRWb<0b01010, 1, 0, 0b010, "cv.cplxmul.r.div2">;
466 def CV_CPLXMUL_I_DIV2 : CVSIMDRRWb<0b01010, 1, 1, 0b010, "cv.cplxmul.i.div2">;
477 def CV_SUBROTMJ_DIV2 : CVSIMDRR<0b01100, 1, 0, 0b010, "cv.subrotmj.div2">;
481 def CV_ADD_DIV2 : CVSIMDRR<0b01101, 1, 0, 0b010, "cv.add.div2">;
485 def CV_SUB_DIV2 : CVSIMDRR<0b01110, 1, 0, 0b010, "cv.sub.div2">;
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/
H A Dqman.txt162 clock-output-names = "platform-pll", "platform-pll-div2";
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam33xx-clocks.dtsi270 dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
443 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
H A Dam43xx-clocks.dtsi519 dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex5.dtsi91 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
H A Dsocfpga_agilex.dtsi111 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8qm.dtsi577 mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm4450.dtsi36 bi_tcxo_div2: bi-tcxo-div2-clk {
H A Dsm8650.dtsi48 bi_tcxo_div2: bi-tcxo-div2-clk {
57 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
H A Dsm8550.dtsi46 bi_tcxo_div2: bi-tcxo-div2-clk {
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
H A Dx1e80100.dtsi45 bi_tcxo_div2: bi-tcxo-div2-clk {
54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi130 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30.dtsi1299 level2_trip: cpu-div2-throttle {