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Searched refs:clkdef (Results 1 – 25 of 129) sorted by relevance

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/freebsd/sys/arm64/freescale/imx/
H A Dimx_ccm.h82 .clkdef.id = _id, \
83 .clkdef.name = _name, \
84 .clkdef.parent_names = NULL, \
85 .clkdef.parent_cnt = 0, \
86 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
95 .clkdef.id = _id, \
96 .clkdef.name = _name, \
97 .clkdef.parent_names = _pn, \
98 .clkdef.parent_cnt = nitems(_pn), \
99 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_cru.h64 .clkdef.id = _id, \
65 .clkdef.name = _name, \
66 .clkdef.parent_names = NULL, \
67 .clkdef.parent_cnt = 0, \
68 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
78 .clkdef.id = _id, \
79 .clkdef.name = _name, \
80 .clkdef.parent_names = (const char *[]){_pname}, \
81 .clkdef.parent_cnt = 1, \
82 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
[all …]
H A Drk_clk_armclk.c219 rk_clk_armclk_register(struct clkdom *clkdom, struct rk_clk_armclk_def *clkdef) in rk_clk_armclk_register() argument
225 &clkdef->clkdef); in rk_clk_armclk_register()
231 sc->muxdiv_offset = clkdef->muxdiv_offset; in rk_clk_armclk_register()
233 sc->mux_shift = clkdef->mux_shift; in rk_clk_armclk_register()
234 sc->mux_width = clkdef->mux_width; in rk_clk_armclk_register()
235 sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift; in rk_clk_armclk_register()
237 sc->div_shift = clkdef->div_shift; in rk_clk_armclk_register()
238 sc->div_width = clkdef->div_width; in rk_clk_armclk_register()
239 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_armclk_register()
241 sc->flags = clkdef->flags; in rk_clk_armclk_register()
[all …]
/freebsd/sys/dev/clk/xilinx/
H A Dzynqmp_clock.c89 struct clknode_init_def clkdef; member
136 zynqmp_clk_register(struct clkdom *clkdom, device_t fw, struct zynqmp_clk *clkdef) in zynqmp_clk_register() argument
147 if (ZYNQMP_GET_NODE_TYPE(clkdef->topology[i]) == CLK_NODE_TYPE_NULL) in zynqmp_clk_register()
150 zynqclk->id = clkdef->clkdef.id; in zynqmp_clk_register()
153 zynqclk->parent_cnt = clkdef->clkdef.parent_cnt; in zynqmp_clk_register()
154 zynqclk->parent_names = clkdef->clkdef.parent_names; in zynqmp_clk_register()
162 switch (ZYNQMP_GET_NODE_TYPE(clkdef->topology[i])) { in zynqmp_clk_register()
164 asprintf(&clkname, M_DEVBUF, "%s_mux", clkdef->clkdef.name); in zynqmp_clk_register()
169 asprintf(&clkname, M_DEVBUF, "%s_pll", clkdef->clkdef.name); in zynqmp_clk_register()
174 asprintf(&clkname, M_DEVBUF, "%s_fixed", clkdef->clkdef.name); in zynqmp_clk_register()
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_car.c67 .clkdef.id = _id, \
68 .clkdef.name = cname, \
69 .clkdef.parent_names = plists, \
70 .clkdef.parent_cnt = nitems(plists), \
71 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
80 .clkdef.id = _id, \
81 .clkdef.name = cname, \
82 .clkdef.parent_names = (const char *[]){plist}, \
83 .clkdef.parent_cnt = 1, \
84 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
[all …]
/freebsd/sys/arm64/qoriq/clk/
H A Dqoriq_clk_pll.c104 const struct qoriq_clk_pll_def *clkdef) in qoriq_clk_pll_register() argument
115 &clkdef->clkdef); in qoriq_clk_pll_register()
120 sc->mask = clkdef->mask; in qoriq_clk_pll_register()
121 sc->shift = clkdef->shift; in qoriq_clk_pll_register()
122 sc->flags = clkdef->flags; in qoriq_clk_pll_register()
123 sc->offset = clkdef->offset; in qoriq_clk_pll_register()
127 parent_name = clkdef->clkdef.name; in qoriq_clk_pll_register()
129 def.clkdef.parent_names = &parent_name; in qoriq_clk_pll_register()
130 def.clkdef.parent_cnt = 1; in qoriq_clk_pll_register()
131 def.clkdef.name = namebuf; in qoriq_clk_pll_register()
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Daw_clk_prediv_mux.c138 aw_clk_prediv_mux_register(struct clkdom *clkdom, struct aw_clk_prediv_mux_def *clkdef) in aw_clk_prediv_mux_register() argument
143 clk = clknode_create(clkdom, &aw_prediv_mux_clknode_class, &clkdef->clkdef); in aw_clk_prediv_mux_register()
149 sc->offset = clkdef->offset; in aw_clk_prediv_mux_register()
151 sc->mux_shift = clkdef->mux_shift; in aw_clk_prediv_mux_register()
152 sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift; in aw_clk_prediv_mux_register()
154 sc->div.shift = clkdef->div.shift; in aw_clk_prediv_mux_register()
155 sc->div.mask = ((1 << clkdef->div.width) - 1) << sc->div.shift; in aw_clk_prediv_mux_register()
156 sc->div.value = clkdef->div.value; in aw_clk_prediv_mux_register()
157 sc->div.cond_shift = clkdef->div.cond_shift; in aw_clk_prediv_mux_register()
158 sc->div.cond_mask = ((1 << clkdef->div.cond_width) - 1) << sc->div.shift; in aw_clk_prediv_mux_register()
[all …]
H A Daw_clk_mipi.c242 aw_clk_mipi_register(struct clkdom *clkdom, struct aw_clk_mipi_def *clkdef) in aw_clk_mipi_register() argument
247 clk = clknode_create(clkdom, &aw_mipi_clknode_class, &clkdef->clkdef); in aw_clk_mipi_register()
253 sc->offset = clkdef->offset; in aw_clk_mipi_register()
255 sc->k.shift = clkdef->k.shift; in aw_clk_mipi_register()
256 sc->k.width = clkdef->k.width; in aw_clk_mipi_register()
258 sc->k.value = clkdef->k.value; in aw_clk_mipi_register()
259 sc->k.flags = clkdef->k.flags; in aw_clk_mipi_register()
260 sc->k.min_value = clkdef->k.min_value; in aw_clk_mipi_register()
262 sc->m.shift = clkdef->m.shift; in aw_clk_mipi_register()
263 sc->m.width = clkdef->m.width; in aw_clk_mipi_register()
[all …]
H A Daw_clk_nm.c302 aw_clk_nm_register(struct clkdom *clkdom, struct aw_clk_nm_def *clkdef) in aw_clk_nm_register() argument
307 clk = clknode_create(clkdom, &aw_nm_clknode_class, &clkdef->clkdef); in aw_clk_nm_register()
313 sc->offset = clkdef->offset; in aw_clk_nm_register()
315 sc->m.shift = clkdef->m.shift; in aw_clk_nm_register()
316 sc->m.width = clkdef->m.width; in aw_clk_nm_register()
318 sc->m.value = clkdef->m.value; in aw_clk_nm_register()
319 sc->m.flags = clkdef->m.flags; in aw_clk_nm_register()
321 sc->n.shift = clkdef->n.shift; in aw_clk_nm_register()
322 sc->n.width = clkdef->n.width; in aw_clk_nm_register()
324 sc->n.value = clkdef->n.value; in aw_clk_nm_register()
[all …]
H A Daw_clk_nkmp.c358 aw_clk_nkmp_register(struct clkdom *clkdom, struct aw_clk_nkmp_def *clkdef) in aw_clk_nkmp_register() argument
363 clk = clknode_create(clkdom, &aw_nkmp_clknode_class, &clkdef->clkdef); in aw_clk_nkmp_register()
369 sc->offset = clkdef->offset; in aw_clk_nkmp_register()
371 sc->n.shift = clkdef->n.shift; in aw_clk_nkmp_register()
372 sc->n.width = clkdef->n.width; in aw_clk_nkmp_register()
373 sc->n.mask = ((1 << clkdef->n.width) - 1) << sc->n.shift; in aw_clk_nkmp_register()
374 sc->n.value = clkdef->n.value; in aw_clk_nkmp_register()
375 sc->n.flags = clkdef->n.flags; in aw_clk_nkmp_register()
377 sc->k.shift = clkdef->k.shift; in aw_clk_nkmp_register()
378 sc->k.width = clkdef->k.width; in aw_clk_nkmp_register()
[all …]
H A Daw_clk_nmm.c236 aw_clk_nmm_register(struct clkdom *clkdom, struct aw_clk_nmm_def *clkdef) in aw_clk_nmm_register() argument
241 clk = clknode_create(clkdom, &aw_nmm_clknode_class, &clkdef->clkdef); in aw_clk_nmm_register()
247 sc->offset = clkdef->offset; in aw_clk_nmm_register()
249 sc->n.shift = clkdef->n.shift; in aw_clk_nmm_register()
250 sc->n.width = clkdef->n.width; in aw_clk_nmm_register()
252 sc->n.value = clkdef->n.value; in aw_clk_nmm_register()
253 sc->n.flags = clkdef->n.flags; in aw_clk_nmm_register()
255 sc->m0.shift = clkdef->m0.shift; in aw_clk_nmm_register()
256 sc->m0.width = clkdef->m0.width; in aw_clk_nmm_register()
258 sc->m0.value = clkdef->m0.value; in aw_clk_nmm_register()
[all …]
H A Daw_clk_frac.c348 aw_clk_frac_register(struct clkdom *clkdom, struct aw_clk_frac_def *clkdef) in aw_clk_frac_register() argument
353 clk = clknode_create(clkdom, &aw_frac_clknode_class, &clkdef->clkdef); in aw_clk_frac_register()
359 sc->offset = clkdef->offset; in aw_clk_frac_register()
361 sc->m.shift = clkdef->m.shift; in aw_clk_frac_register()
362 sc->m.width = clkdef->m.width; in aw_clk_frac_register()
364 sc->m.value = clkdef->m.value; in aw_clk_frac_register()
365 sc->m.flags = clkdef->m.flags; in aw_clk_frac_register()
367 sc->n.shift = clkdef->n.shift; in aw_clk_frac_register()
368 sc->n.width = clkdef->n.width; in aw_clk_frac_register()
370 sc->n.value = clkdef->n.value; in aw_clk_frac_register()
[all …]
H A Daw_clk_np.c224 aw_clk_np_register(struct clkdom *clkdom, struct aw_clk_np_def *clkdef) in aw_clk_np_register() argument
229 clk = clknode_create(clkdom, &aw_np_clknode_class, &clkdef->clkdef); in aw_clk_np_register()
235 sc->offset = clkdef->offset; in aw_clk_np_register()
237 sc->n.shift = clkdef->n.shift; in aw_clk_np_register()
238 sc->n.width = clkdef->n.width; in aw_clk_np_register()
240 sc->n.value = clkdef->n.value; in aw_clk_np_register()
241 sc->n.flags = clkdef->n.flags; in aw_clk_np_register()
243 sc->p.shift = clkdef->p.shift; in aw_clk_np_register()
244 sc->p.width = clkdef->p.width; in aw_clk_np_register()
246 sc->p.value = clkdef->p.value; in aw_clk_np_register()
[all …]
/freebsd/sys/arm/mv/clk/
H A Dperiph_clk_d.c77 a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs, in a37x0_periph_d_register_full_clk_dd()
85 a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
91 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
98 parent_names[1] = div2->clkdef.name; in a37x0_periph_d_register_full_clk_dd()
100 a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT); in a37x0_periph_d_register_full_clk_dd()
106 a37x0_periph_set_props(&gate->clkdef, &clk_mux->clkdef.name, 1); in a37x0_periph_d_register_full_clk_dd()
140 a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs, in a37x0_periph_d_register_full_clk()
147 a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1); in a37x0_periph_d_register_full_clk()
154 parent_names[1] = div->clkdef.name; in a37x0_periph_d_register_full_clk()
156 a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT); in a37x0_periph_d_register_full_clk()
[all …]
H A Darmada38x_gateclk.c67 .clkdef = {
76 .clkdef = {
85 .clkdef = {
94 .clkdef = {
103 .clkdef = {
112 .clkdef = {
121 .clkdef = {
130 .clkdef = {
139 .clkdef = {
148 .clkdef
[all...]
H A Dperiph_clk_mux_gate.c73 fixed.clkdef.id = A37x0_INTERNAL_CLK_ID(dev_id, FIXED1_POS); in a37x0_periph_register_mux_gate()
74 fixed.clkdef.parent_names = &device_def->common_def.pname; in a37x0_periph_register_mux_gate()
75 fixed.clkdef.parent_cnt = 1; in a37x0_periph_register_mux_gate()
76 fixed.clkdef.flags = 0x0; in a37x0_periph_register_mux_gate()
86 parent_names[1] = fixed.clkdef.name; in a37x0_periph_register_mux_gate()
88 a37x0_periph_set_props(&mux->clkdef, parent_names, PARENT_CNT); in a37x0_periph_register_mux_gate()
94 a37x0_periph_set_props(&gate->clkdef, &mux->clkdef.name, 1); in a37x0_periph_register_mux_gate()
126 fixed1->clkdef.parent_names = &device_def->common_def.pname; in a37x0_periph_register_mux_gate_fixed()
127 fixed1->clkdef.id = A37x0_INTERNAL_CLK_ID(dev_id, FIXED1_POS); in a37x0_periph_register_mux_gate_fixed()
128 fixed1->clkdef.flags = 0x0; in a37x0_periph_register_mux_gate_fixed()
[all …]
H A Dperiph.c56 mux->clkdef.id = id; in a37x0_periph_create_mux()
60 printf("Failed to create %s: %d\n", mux->clkdef.name, error); in a37x0_periph_create_mux()
73 div->clkdef.id = id; in a37x0_periph_create_div()
77 printf("Failed to register %s: %d\n", div->clkdef.name, error); in a37x0_periph_create_div()
90 gate->clkdef.id = id; in a37x0_periph_create_gate()
94 printf("Failed to create %s:%d\n", gate->clkdef.name, error); in a37x0_periph_create_gate()
102 a37x0_periph_set_props(struct clknode_init_def *clkdef, in a37x0_periph_set_props() argument
106 clkdef->parent_names = parent_names; in a37x0_periph_set_props()
107 clkdef->parent_cnt = parent_cnt; in a37x0_periph_set_props()
/freebsd/sys/arm/mv/
H A Dmv_cp110_clock.c56 .clkdef.id = CP110_PLL_0,
64 .clkdef.id = CP110_PPV2_CORE,
65 .clkdef.parent_cnt = 1,
71 .clkdef.id = CP110_X2CORE,
72 .clkdef.parent_cnt = 1,
81 .clkdef.id = CP110_CORE,
82 .clkdef.parent_cnt = 1,
88 .clkdef.id = CP110_SDIO,
89 .clkdef.parent_cnt = 1,
211 cp110_clk_pll_0.clkdef.name = pll0_name; in mv_cp110_clock_attach()
[all …]
H A Dmv_ap806_clock.c51 .clkdef.id = 0,
52 .clkdef.name = "ap806-cpu-cluster-0",
57 .clkdef.id = 1,
58 .clkdef.name = "ap806-cpu-cluster-1",
63 .clkdef.id = 2,
64 .clkdef.name = "ap806-fixed",
72 .clkdef.id = 3,
73 .clkdef.name = "ap806-mss",
74 .clkdef.parent_names = mss_parents,
75 .clkdef.parent_cnt = 1,
[all …]
/freebsd/sys/dev/qcom_gcc/
H A Dqcom_gcc_ipq4018_clock.c68 .clkdef.id = _id, \
69 .clkdef.name = cname, \
70 .clkdef.parent_names = NULL, \
71 .clkdef.parent_cnt = 0, \
72 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
79 .clkdef.id = _id, \
80 .clkdef.name = _cname, \
81 .clkdef.parent_names = NULL, \
82 .clkdef.parent_cnt = 0, \
83 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_car.c66 .clkdef.id = _id, \
67 .clkdef.name = cname, \
68 .clkdef.parent_names = plists, \
69 .clkdef.parent_cnt = nitems(plists), \
70 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
79 .clkdef.id = _id, \
80 .clkdef.name = cname, \
81 .clkdef.parent_names = (const char *[]){plist}, \
82 .clkdef.parent_cnt = 1, \
83 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
[all …]
/freebsd/sys/arm/ti/clk/
H A Dti_clk_dpll.c294 ti_clknode_dpll_register(struct clkdom *clkdom, struct ti_clk_dpll_def *clkdef) in ti_clknode_dpll_register() argument
299 clk = clknode_create(clkdom, &ti_dpll_clknode_class, &clkdef->clkdef); in ti_clknode_dpll_register()
305 sc->ti_clkmode_offset = clkdef->ti_clkmode_offset; in ti_clknode_dpll_register()
306 sc->ti_clkmode_flags = clkdef->ti_clkmode_flags; in ti_clknode_dpll_register()
307 sc->ti_idlest_offset = clkdef->ti_idlest_offset; in ti_clknode_dpll_register()
308 sc->ti_clksel_offset = clkdef->ti_clksel_offset; in ti_clknode_dpll_register()
310 sc->n.shift = clkdef->ti_clksel_mult.shift; in ti_clknode_dpll_register()
311 sc->n.mask = clkdef->ti_clksel_mult.mask; in ti_clknode_dpll_register()
312 sc->n.width = clkdef->ti_clksel_mult.width; in ti_clknode_dpll_register()
313 sc->n.value = clkdef->ti_clksel_mult.value; in ti_clknode_dpll_register()
[all …]
/freebsd/sys/dev/clk/
H A Dclk_fixed.c120 clknode_fixed_register(struct clkdom *clkdom, struct clk_fixed_def *clkdef) in clknode_fixed_register() argument
125 clk = clknode_create(clkdom, &clknode_fixed_class, &clkdef->clkdef); in clknode_fixed_register()
130 sc->fixed_flags = clkdef->fixed_flags; in clknode_fixed_register()
131 sc->freq = clkdef->freq; in clknode_fixed_register()
132 sc->mult = clkdef->mult; in clknode_fixed_register()
133 sc->div = clkdef->div; in clknode_fixed_register()
187 def->clkdef.id = 1; in clk_fixed_init_fixed()
202 def->clkdef.id = 1; in clk_fixed_init_fixed_factor()
213 def->clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP, M_WAITOK); in clk_fixed_init_fixed_factor()
214 def->clkdef.parent_names[0] = clk_get_name(parent); in clk_fixed_init_fixed_factor()
[all …]
/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_branch2.c259 struct qcom_clk_branch2_def *clkdef) in qcom_clk_branch2_register() argument
264 if (clkdef->flags & QCOM_CLK_BRANCH2_FLAGS_CRITICAL) in qcom_clk_branch2_register()
265 clkdef->clkdef.flags |= CLK_NODE_CANNOT_STOP; in qcom_clk_branch2_register()
268 &clkdef->clkdef); in qcom_clk_branch2_register()
275 sc->enable_offset = clkdef->enable_offset; in qcom_clk_branch2_register()
276 sc->enable_shift = clkdef->enable_shift; in qcom_clk_branch2_register()
277 sc->halt_reg = clkdef->halt_reg; in qcom_clk_branch2_register()
278 sc->hwcg_reg = clkdef->hwcg_reg; in qcom_clk_branch2_register()
279 sc->hwcg_bit = clkdef->hwcg_bit; in qcom_clk_branch2_register()
280 sc->halt_check_type = clkdef->halt_check_type; in qcom_clk_branch2_register()
[all …]
/freebsd/sys/riscv/sifive/
H A Dsifive_prci.c185 .clkdef.id = FU540_PRCI_TLCLK,
186 .clkdef.name = "tlclk",
187 .clkdef.parent_names = (const char *[]){"coreclk"},
188 .clkdef.parent_cnt = 1,
189 .clkdef.flags = CLK_NODE_STATIC_STRINGS,
247 .clkdef.id = FU740_PRCI_TLCLK,
248 .clkdef.name = "tlclk",
249 .clkdef.parent_names = (const char *[]){"coreclk"},
250 .clkdef.parent_cnt = 1,
251 .clkdef.flags = CLK_NODE_STATIC_STRINGS,
[all …]

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