Searched refs:cascaded (Results 1 – 25 of 47) sorted by relevance
12
17 it is considered as an interrupt controller cascaded to the SoC one.34 interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
32 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
40 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
35 may be cascaded into the core interrupt controller. The megamodule PIC38 interrupt sources, individual megamodule interrupts may be cascaded to39 the core interrupt controller. When an individual interrupt is cascaded,
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
36 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
168 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */175 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
176 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */188 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
24 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
69 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
86 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
114 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
61 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
410 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */423 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
83 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
145 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
151 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
382 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */394 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
297 #define MANIP_IS_CASCADED(h_Manip) (((t_FmPcdManip *)h_Manip)->cascaded)509 bool cascaded; member
16 The GPIO module may serve as another interrupt controller (cascaded to
47 /* Secondary IC cascaded to intc0 */
51 /* Secondary IC cascaded to intc0 */
50 /* Secondary IC cascaded to intc0 */
59 /* We are not cascaded */