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Searched refs:bus_write_1 (Results 1 – 25 of 86) sorted by relevance

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/freebsd/sys/dev/ichsmb/
H A Dichsmb.c122 bus_write_1(sc->io_res, ICH_HST_STA, 0xff); in ichsmb_attach()
177 bus_write_1(sc->io_res, ICH_XMIT_SLVA, in ichsmb_quick()
180 bus_write_1(sc->io_res, ICH_HST_CNT, in ichsmb_quick()
203 bus_write_1(sc->io_res, ICH_XMIT_SLVA, in ichsmb_sendb()
205 bus_write_1(sc->io_res, ICH_HST_CMD, byte); in ichsmb_sendb()
206 bus_write_1(sc->io_res, ICH_HST_CNT, in ichsmb_sendb()
225 bus_write_1(sc->io_res, ICH_XMIT_SLVA, in ichsmb_recvb()
227 bus_write_1(sc->io_res, ICH_HST_CNT, in ichsmb_recvb()
248 bus_write_1(sc->io_res, ICH_XMIT_SLVA, in ichsmb_writeb()
250 bus_write_1(sc->io_res, ICH_HST_CMD, cmd); in ichsmb_writeb()
[all …]
/freebsd/sys/dev/intpm/
H A Dintpm.c127 bus_write_1(res, 0, reg); /* Index */ in amd_pmio_read()
364 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN); in intsmb_attach()
432 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0); in intsmb_free()
435 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS, in intsmb_free()
454 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, in intsmb_intr()
480 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS, in intsmb_slvintr()
498 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, in intsmb_alrintr()
509 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB); in intsmb_alrintr()
520 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, in intsmb_alrintr()
540 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp); in intsmb_start()
[all …]
/freebsd/sys/dev/puc/
H A Dpucdata.c1789 bus_write_1(bar->b_res, REG_SPR, REG_ACR); in puc_config_advantech()
1790 bus_write_1(bar->b_res, REG_ICR, acr); in puc_config_advantech()
1902 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB); in puc_config_quatech()
1903 bus_write_1(bar->b_res, REG_SPR, 0); in puc_config_quatech()
1905 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); in puc_config_quatech()
1907 bus_write_1(bar->b_res, REG_LCR, 0); in puc_config_quatech()
1994 bus_write_1(bar->b_res, 0x250, 0x89); in puc_config_syba()
1995 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
1996 bus_write_1(bar->b_res, 0x3f0, 0x87); in puc_config_syba()
2000 bus_write_1(bar->b_res, efir, 0x09); in puc_config_syba()
[all …]
/freebsd/sys/dev/ppc/
H A Dppcreg.h163 #define w_dtr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_DTR, byte))
164 #define w_str(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_STR, byte))
165 #define w_ctr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_CTR, byte))
167 #define w_epp_A(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_ADDR, byte))
168 #define w_epp_D(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_DATA, byte))
169 #define w_ecr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_ECR, byte))
170 #define w_fifo(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_D_FIFO, byte))
/freebsd/sys/powerpc/amigaone/
H A Dcpld_a1222.c133 bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_H, addr); in cpld_write()
134 bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_L, addr); in cpld_write()
136 bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_H, addr); in cpld_write()
137 bus_write_1(sc->sc_mem, CPLD_MEM_DATA, data); in cpld_write()
144 bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_H, addr); in cpld_read()
145 bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_L, addr); in cpld_read()
147 bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_H, addr); in cpld_read()
162 bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_H, addr); in cpld_read_pair()
165 bus_write_1(sc->sc_mem, CPLD_MEM_ADDR_H, addr + 1); in cpld_read_pair()
/freebsd/sys/dev/mlx/
H A Dmlxreg.h81 #define MLX_V3_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V3_MAILBOX + idx, val)
85 #define MLX_V3_PUT_IDBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_IDBR, val)
87 #define MLX_V3_PUT_ODBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_ODBR, val)
88 #define MLX_V3_PUT_IER(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_IER, val)
90 #define MLX_V3_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V3_FWERROR, val)
118 #define MLX_V4_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V4_MAILBOX + idx, val)
127 #define MLX_V4_PUT_FWERROR(sc, val) bus_write_1(sc->mlx_mem, MLX_V4_FWERROR, val)
163 #define MLX_V5_PUT_MAILBOX(sc, idx, val) bus_write_1(sc->mlx_mem, MLX_V5_MAILBOX + idx, val)
167 #define MLX_V5_PUT_IDBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_IDBR, val)
169 #define MLX_V5_PUT_ODBR(sc, val) bus_write_1(sc->mlx_mem, MLX_V5_ODBR, val)
[all …]
/freebsd/sys/dev/glxiic/
H A Dglxiic.c492 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT | in glxiic_read_status_locked()
509 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, in glxiic_stop_locked()
522 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, in glxiic_stop_locked()
658 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data); in glxiic_state_slave_tx_callback()
739 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave); in glxiic_state_master_addr_callback()
744 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, in glxiic_state_master_addr_callback()
773 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, in glxiic_state_master_tx_callback()
782 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++); in glxiic_state_master_tx_callback()
815 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, in glxiic_state_master_rx_callback()
835 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, in glxiic_state_master_rx_callback()
[all …]
/freebsd/sys/dev/superio/
H A Dsuperio.c110 bus_write_1(res, 0, reg); in sio_read()
129 bus_write_1(res, 0, reg); in sio_write()
130 bus_write_1(res, 1, val); in sio_write()
196 bus_write_1(res, 0, 0x87); in ite_conf_enter()
197 bus_write_1(res, 0, 0x01); in ite_conf_enter()
198 bus_write_1(res, 0, 0x55); in ite_conf_enter()
199 bus_write_1(res, 0, port == 0x2e ? 0x55 : 0xaa); in ite_conf_enter()
217 bus_write_1(res, 0, 0x87); in nvt_conf_enter()
218 bus_write_1(res, 0, 0x87); in nvt_conf_enter()
224 bus_write_1(res, 0, 0xaa); in nvt_conf_exit()
[all …]
/freebsd/sys/powerpc/powermac/
H A Dmacgpio.c294 bus_write_1(sc->sc_gpios,dinfo->gpio_num,val); in macgpio_activate_resource()
316 bus_write_1(sc->sc_gpios,dinfo->gpio_num,val); in macgpio_deactivate_resource()
349 bus_write_1(sc->sc_gpios,dinfo->gpio_num,val); in macgpio_write()
390 bus_write_1(sc->sc_gpios, GPIO_BASE + i, sc->sc_saved_gpios[i]); in macgpio_resume()
392 bus_write_1(sc->sc_gpios, GPIO_EXTINT_BASE + i, sc->sc_saved_extint_gpios[i]); in macgpio_resume()
H A Dmacio.c744 bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0f, 5); in macio_enable_wireless()
746 bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0f, 4); in macio_enable_wireless()
754 bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0b, 0); in macio_enable_wireless()
755 bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0a, 0x28); in macio_enable_wireless()
756 bus_write_1(sc->sc_memr, KEYLARGO_EXTINT_GPIO_REG_BASE + 0x0d, 0x28); in macio_enable_wireless()
757 bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0d, 0x28); in macio_enable_wireless()
758 bus_write_1(sc->sc_memr, KEYLARGO_GPIO_BASE + 0x0e, 0x28); in macio_enable_wireless()
783 bus_write_1(sc->sc_memr, sc->sc_timebase, 4); in macio_freeze_timebase()
785 bus_write_1(sc->sc_memr, sc->sc_timebase, 0); in macio_freeze_timebase()
H A Datibl.c169 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f)); in atibl_pll_rreg()
190 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, in atibl_pll_wreg()
/freebsd/sys/dev/dpaa2/
H A Ddpaa2_swp.c881 bus_write_1(map, in dpaa2_swp_enq_mult()
899 bus_write_1(map, in dpaa2_swp_enq_mult()
905 bus_write_1(map, in dpaa2_swp_enq_mult()
973 bus_write_1(map, offset + i, cmd_pdat8[i]); in dpaa2_swp_exec_br_command()
977 bus_write_1(map, offset, c->verb | RAR_VB(rar) | buf_num); in dpaa2_swp_exec_br_command()
983 bus_write_1(map, offset, c->verb | RAR_VB(rar) | buf_num); in dpaa2_swp_exec_br_command()
1025 bus_write_1(map, offset + i, p8[i]); in dpaa2_swp_exec_vdc_command_locked()
1029 bus_write_1(map, offset, c->verb | swp->vdq.valid_bit); in dpaa2_swp_exec_vdc_command_locked()
1036 bus_write_1(map, offset, c->verb | swp->vdq.valid_bit); in dpaa2_swp_exec_vdc_command_locked()
1108 bus_write_1(map, offset + i, cmd_pdat8[i]); in dpaa2_swp_send_mgmt_command()
[all …]
/freebsd/sys/dev/gpio/
H A Dpl061.c153 bus_write_1(sc->sc_mem_res, a, tmp); in mask_and_set()
212 bus_write_1(sc->sc_mem_res, PL061_PIN_TO_ADDR(pin), d); in pl061_pin_set()
230 bus_write_1(sc->sc_mem_res, PL061_PIN_TO_ADDR(pin), d); in pl061_pin_toggle()
385 bus_write_1(sc->sc_mem_res, PL061_INTCLR, mask); in pl061_pic_post_filter()
397 bus_write_1(sc->sc_mem_res, PL061_INTCLR, mask); in pl061_pic_post_ithread()
464 bus_write_1(sc->sc_mem_res, PL061_INTMASK, 0); in pl061_attach()
/freebsd/sys/dev/pcf/
H A Dpcfvar.h101 bus_write_1(sc->res_ioport, 0, data); in pcf_set_S0()
109 bus_write_1(sc->res_ioport, 1, data); in pcf_set_S1()
/freebsd/sys/dev/ncthwm/
H A Dncthwm.c121 bus_write_1(sc->iores, 0, reg); in ncthwm_write()
122 bus_write_1(sc->iores, 1, val); in ncthwm_write()
128 bus_write_1(sc->iores, 0, reg); in ncthwm_read()
/freebsd/sys/dev/asmc/
H A Dasmcvar.h60 bus_write_1(sc->sc_ioport, 0x00, val)
68 bus_write_1(sc->sc_ioport, 0x04, val)
/freebsd/sys/powerpc/pseries/
H A Dxics.c264 bus_write_1(sc->mem[i], 4, 0xff); in xicp_attach()
265 bus_write_1(sc->mem[i], 12, 0xff); in xicp_attach()
404 bus_write_1(regs, 12, 0xff); in xicp_dispatch()
508 bus_write_1(xicp_mem_for_cpu(cpu), 12, XICP_PRIORITY); in xicp_ipi()
/freebsd/sys/dev/ipmi/
H A Dipmivars.h216 bus_write_1((sc)->ipmi_io_res[0], (sc)->ipmi_io_spacing * (x), value)
222 bus_write_1((sc)->ipmi_io_res[(x)], 0, value)
/freebsd/sys/dev/hdmi/
H A Ddwc_hdmi.h54 bus_write_1(sc->sc_mem_res, off << sc->sc_reg_shift, val); in WR1()
/freebsd/sys/dev/amdsbwd/
H A Damdsbwd.c135 bus_write_1(res, 0, reg); /* Index */ in pmio_read()
142 bus_write_1(res, 0, reg); /* Index */ in pmio_write()
143 bus_write_1(res, 1, val); /* Data */ in pmio_write()
/freebsd/sys/dev/tpm/
H A Dtpm_bus.c68 bus_write_1(sc->mem_res, off, val); in tpm_write_1()
/freebsd/tools/bus_space/C/
H A Dlibbus.h36 int bus_write_1(int rid, long ofs, uint8_t val);
/freebsd/sys/dev/sram/
H A Dmmio_sram.c142 bus_write_1(sc->res[0], offset, val); in mmio_sram_write_1()
/freebsd/sys/dev/ida/
H A Didavar.h44 bus_write_1((ida)->regs, port, val)
/freebsd/sys/dev/fxp/
H A Dif_fxpvar.h247 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)

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